In this paper a Qi-standard compliant compact wireless power charger system, composed of a wireless power transmitter and a wireless power receiver, is presented. The developed system aims to be compliant with the lat...
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In this paper a Qi-standard compliant compact wireless power charger system, composed of a wireless power transmitter and a wireless power receiver, is presented. The developed system aims to be compliant with the latest revision of Wireless Power Consortium's directives and uses a full-bridge resonant inverter as the main power transmitter architecture. The wireless power transmitter and receiver have been designed with ultra low power and high efficiency electronics components thereby maximizing the overall power transfer efficiency.
Visual search has seen many improvements over the years, but its application on video content is still an open research problem and it is often limited to still images. Based on the tools devised by the standardizatio...
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Visual search has seen many improvements over the years, but its application on video content is still an open research problem and it is often limited to still images. Based on the tools devised by the standardization group MPEG CDVS, we developed a processing flow that processes at nearly real-time a video acquired with a low cost imager and performs content search and retrieval of the top match from a local database. To allow efficient interest point detection, we used a GPU accelerated SIFT library. To process the video frames efficiently, we developed a new dataflow processing which allows switching between object searching, retrieving and tracking in order to keep at minimum the number of queries sent to the database. A search into a local database is performed only when no object has been recognized, and once a good match has been found, the algorithm switches to tracking mode.
Wireless Sensor Networks are destined to play a fundamental role in the next-generation Internet, which will be characterized by the Machine-to-Machine paradigm, according to which, embedded devices will actively exch...
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Wireless Sensor Networks are destined to play a fundamental role in the next-generation Internet, which will be characterized by the Machine-to-Machine paradigm, according to which, embedded devices will actively exchange information, thus enabling the development of innovative applications. It will contribute to assert the concept of Internet of Things, where end-to-end security represents a key issue. In such context, it is very important to understand which protocols are able to provide the right level of security without burdening the limited resources of constrained networks. This paper presents a performance comparison between two of the most widely used security protocols: IPSec and DTLS. We provide the analysis of their impact on the resources of embedded devices. For this purpose, we have modified existing implementations of both protocols to make them properly run on our hardware platforms, and we have performed an extensive experimental evaluation study. The achieved results are not a consequence of a classical simulation campaign, but they have been obtained in a real scenario that uses software and hardware typical of the current technological developments. Therefore, they can help network designers to identify the most appropriate secure mechanism for end-to-end IP communications involving constrained devices.
True Random Number Generators (TRNG) are cryptographic primitives that exploit intrinsic noise sources in electronic devices. Their quality is linked to the underlying technology, activity of the neighboring circuitry...
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True Random Number Generators (TRNG) are cryptographic primitives that exploit intrinsic noise sources in electronic devices. Their quality is linked to the underlying technology, activity of the neighboring circuitry and device environment (temperature, power supply, electromagnetic emanations). Consequently, when comparing TRNGs, they should be tested in identical technology, system architecture and operating conditions. We present a unified hardware platform and related open source tools aimed at fair benchmarking of TRNGs implemented in different FPGA technologies. The platform is accessible remotely. Designers can download related tools from the web site and they can upload their configuration bitstream to the remote FPGA and download random data generated in the same hardware and in the same conditions as other concurrent designs and state-of-the-art generators. The proposed tools were approved in many applications and they guarantee safe acquisition of random sequences at data rates of up to 400 Mbits/s.
Many-core architectures are becoming increasingly popular due to advances in open programming environments. Typical architectures are Graphics Processing Units (GPUs) and Homogenous Computing Fabrics, offering high co...
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3D Video and related technologies like view synthesis, 2D-3D video conversions rely heavily on depth/disparity maps extracted from stereo video content. Innovative Segment-based depth map extraction chain from stereo ...
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3D Video and related technologies like view synthesis, 2D-3D video conversions rely heavily on depth/disparity maps extracted from stereo video content. Innovative Segment-based depth map extraction chain from stereo video content was proposed in [1] giving good trade-off between quality (exactness to the ground truth) and computational complexity. We accelerated this work further by~150%, both at algorithmic level and by using GP-GPU system (General Purpose processor-Graphics Processing Unit) which is programmed using OpenCL. Our work also compares speedups in terms of cycles consumed GP vs. GPU which goes on to show how GPU can also be utilized for general computations, hence aiding acceleration.
The current trend in Wireless Sensor Networks (WSN) is to use the Internet Protocol (IP) and open standards to achieve native connectivity between smart objects and the Internet, contributing to consolidate the Intern...
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The importance of having an efficient Fast Fourier Transform (FFT) implementation is universally recognized as one of the key enablers for the development of new and more powerful signal processing algorithms. In the ...
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ISBN:
(纸本)9783981080186
The importance of having an efficient Fast Fourier Transform (FFT) implementation is universally recognized as one of the key enablers for the development of new and more powerful signal processing algorithms. In the field of telecommunications, one of its most recent applications is the Orthogonal Frequency Division Multiplexing (OFDM) modulation technique, whose superiority is recognized and endorsed by several standards. However, the horizon of standards is so wide and heterogeneous that a single FFT implementation hardly satisfies them all. In order to have a reusable, easily extensible and reconfigurable solution, most of the baseband processing is moving towards a software implementation: to this end several new Digital Signal Processor (DSP) architectures are emerging, each with its own set of differentiating properties. Within this context, we propose a software implementation of the FFT on the Block Processing Engine (BPE) platform. Several implementations have been investigated, ranging from a single instruction based approach, to others employing several instructions either in parallel or in pipeline. The outcome is a flexible set of solutions that leaves degrees of freedom in terms of computational load, achievable throughput and power consumption. The proposed implementations closely approach the theoretical clock cycles expected by dedicated hardware counterpart, thus making it a concrete alternative.
Visual search for mobile devices relies on transmitting wirelessly image descriptors to a remote server. Hence, descriptors needs to be compressed to reduce bandwidth occupancy and network latency. In this paper, we i...
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Many-core architectures are becoming increasingly popular due to advances in open programming environments. Typical architectures are Graphics Processing Units (GPUs) and Homogenous Computing Fabrics, offering high co...
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Many-core architectures are becoming increasingly popular due to advances in open programming environments. Typical architectures are Graphics Processing Units (GPUs) and Homogenous Computing Fabrics, offering high computing parallelism in order to decrease execution time of computationally intensive algorithms, for example in Computer Vision. In this paper, a low complexity interest point detector has been written in OpenCL language and executed on different desktop and embedded computing platforms. The algorithm performs interest point detection in an image, around which there is enough distinctive information to enable further description. The algorithm has been optimized on the targeted platforms and performance and accuracy comparison has been performed.
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