Aphasia is a cognitive disorder that impairs speech and language. From interviews with aphasic individuals, their caregivers, and speech-language pathologists, the need was identified for a daily planner that allows a...
详细信息
ISBN:
(纸本)9781581137026
Aphasia is a cognitive disorder that impairs speech and language. From interviews with aphasic individuals, their caregivers, and speech-language pathologists, the need was identified for a daily planner that allows aphasic users to independently manage their appointments. We used a participatory design approach to develop ESI Planner (the Enhanced with Sound and Images Planner) for use on a PDA and subsequently evaluated it in a lab study. This methodology was used in order to achieve both usable and adoptable technology. In addition to describing our experience in designing ESI Planner, two main contributions are provided: general guidelines for working with special populations in the development of technology, and design guidelines for accessible handheld technology.
This paper proposes testability enhancements in architectural design for embedded cores-based system-on-a-chip (SoC). There exist methods to ensure correct SoC functionality in both hardware and software, but one of t...
详细信息
This paper proposes testability enhancements in architectural design for embedded cores-based system-on-a-chip (SoC). There exist methods to ensure correct SoC functionality in both hardware and software, but one of the most reliable ways to realize this is through the use of design for testability approaches. Specifically, applications of built-in self-test (BIST) methodology for testing embedded cores are considered in the paper, with specific implementations being targeted towards ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits.
Let G be a simple connected graph where every node is colored either black or white. Consider now the following repetitive process on G: each node recolors itself, at each local time step, with the color held by the m...
详细信息
Global optimization algorithm applied for feedforward neural networks (NN) supervised learning is investigated. The network weights are determined by minimizing the traditional backpropagation error function. The diff...
详细信息
ISBN:
(纸本)0780382781
Global optimization algorithm applied for feedforward neural networks (NN) supervised learning is investigated. The network weights are determined by minimizing the traditional backpropagation error function. The difference is that the optimization based learning algorithm utilizes stochastic technique, based on the use of low discrepancy sequences. This technique searches the parameter space, defined by the network weights, to define initial regions of attraction with candidates for local minima, and then exploits each region to locate the minima, and to determine a global minimum. The proposed technique is initially tested on multimodal mathematical functions and subsequently applied for training NN with moderate size for solving simple benchmark problems. Finally, the results are analysed, discussed, and compared with others.
Beginning undergraduate engineering students need computing skills. A course was developed to support the retention of those undergraduates who were lacking in basic computing skills. This paper discusses the results ...
详细信息
Beginning undergraduate engineering students need computing skills. A course was developed to support the retention of those undergraduates who were lacking in basic computing skills. This paper discusses the results of using novel technologies in an assimilation course. The technologies consisted of autonomous robots that were relatively easy to build and Pocket PCs with an integrated wireless capability in order to access the Internet. The paper includes the background information on the course, technologies, and the applicability. In addition, student experiences with the tools are also covered in the paper.
In deep submicrometer (DSM) design, the interconnect delay becomes equally as or more important than that of logic gates. In particular, to achieve timing closure in DSM design, it is essential to consider the interco...
详细信息
In deep submicrometer (DSM) design, the interconnect delay becomes equally as or more important than that of logic gates. In particular, to achieve timing closure in DSM design, it is essential to consider the interconnect delay at an early stage of the synthesis process. Unfortunately, few successes of achieving a tight link of front-end synthesis to back-end layout have been reported, from a practical point of view, mainly due to the inaccuracy of predicting the layout effects during the synthesis. In this brief, we address a new approach to the problem of synthesis of parallel multiplier circuits combined with the consideration of layout effects. The approach is intended to overcome some of the limitations of the previous works, in which the effects of layout on the synthesis have either not been taken into account or considered only in local and limited ways, or the computation time is extremely large. The proposed approach refines the structure and placement of the circuit by iteratively performing two tasks. Task 1: timing-driven relocation. For a parallel multiplier circuit that was restructured at the prior iteration, we attempt to replace the modules in the structure while retaining the interconnects to find a placement with shorter timing. Task 2: timing-driven resynthesis. We attempt to restructure the interconnect topology of the placement obtained from Task 1 to further reduce the circuit timing, employing two heuristics: a modified version of timing-optimal FA-tree allocation by Stelling et al. (1996), considering interconnect delay, and a critical path-based local interconnect refinement. The iterative mechanism of the two tasks practically tightly integrates the synthesis and placement tasks so that both of the effects of placement on the results of synthesis and the effects of synthesis on the results of placement are taken into account. From experiments using a set of benchmark designs, it is shown that the approach is quite effective and efficient
In this paper, we propose an efficient extension of set partitioning in hierarchical trees (SPIHT) for very low bit-rate wavelet based color image coding. Since the chrominance components I and Q in YIQ format are suf...
详细信息
In this paper, we propose an efficient extension of set partitioning in hierarchical trees (SPIHT) for very low bit-rate wavelet based color image coding. Since the chrominance components I and Q in YIQ format are sufficiently less significant in terms of energy compared to the luminance component, the trees within each chrominance plane are joined together in the list of insignificant sets (LIS) according to a virtual relationship parent-descendants specific to chrominance components. For generating fully embedded bit stream similar to SPIHT, the proposed method improves the performance of color SPIHT based sch.me, especially for very low bit rate.
Line equation in Cartesian space can be mapped conformally to log-polar. But many the applications of log-polar mapping are using only the peripheral region. This paper presents a method of a Hough transform for a log...
详细信息
Line equation in Cartesian space can be mapped conformally to log-polar. But many the applications of log-polar mapping are using only the peripheral region. This paper presents a method of a Hough transform for a log-polar mapped edge image that includes both foveal and peripheral visual information. It is shown that this method achieves a good performance for line detection on the log-polar space.
The effect of roundoff noise in a digital controller is analysed for a digital feedback control system. An analytical expression for the roundoff noise gain, defined as the ratio between the variances of the output er...
详细信息
The effect of roundoff noise in a digital controller is analysed for a digital feedback control system. An analytical expression for the roundoff noise gain, defined as the ratio between the variances of the output error and the rounding error, is obtained. The problem of identifying the minimum roundoff noise realisations can be solved using an existing procedure. Noting that the optimal realisations are fully parametrised, based on a polynomial operator approach a new sparse controller realisation is derived. This realisation is a generalisation of the direct forms in the classical shift operator and the prevailing delta-operator. It provides more degrees of freedom with which to reduce the roundoff noise. The problem of finding optimal polynomial operators can be solved by an exhaustive search, and a design example is given. It is shown that with the proposed sparse realisation the optimal polynomial operators can outperform the shift- and delta-operators.
A framework on web information representation, extraction and derivation utilising the object-oriented approach is proposed in this paper. We define a structure which is similar to a class in object-oriented design an...
详细信息
ISBN:
(纸本)0769520731
A framework on web information representation, extraction and derivation utilising the object-oriented approach is proposed in this paper. We define a structure which is similar to a class in object-oriented design and programming, and name it as an extended class (eclass). An eclass contains data attributes, member functions/methods, inference rules and presentations, and therefore, facilities information derivation and web presentation. As an object-oriented approach, the framework also supports encapsulation, polymorphism, composition and inheritance. It can be implemented as an extension of an existing object-oriented programming language. An eclass can be extremely effective in content-dependent entity description. It describes a value under its context, consequently, the search engine not only searches the value, but also understands the meaning of the value in the context. We argue that information in any form or complexity can always be represented by instances of eclasses.
暂无评论