In synchronous digital communications it is important to recover the receiver clock, but this is difficult when received data contains long consecutive-zero sequences. We suggest a zero suppression (ZS) algorithm, whi...
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In synchronous digital communications it is important to recover the receiver clock, but this is difficult when received data contains long consecutive-zero sequences. We suggest a zero suppression (ZS) algorithm, which suppresses consecutive-zero sequences of more than k zeros between successive ones in a ciphertext at the sender of a synchronous stream cipher system, and recovers the original message exactly at the receiver. The probability of k consecutive zeros in ciphertext at the sender is 2-k in a synchronous stream cipher without ZS, but 0 with the suggested algorithm. The ZS algorithm does not affect cryptographic security when compared with a synchronous stream cipher without ZS. It is useful for systems which limit consecutive zeros, such as a T1-carrier system (k = 15).
Exact performance analysis of dynamic load-balancing policies for distributed systems is known to be very difficult owing to the facts that the state space is multidimensional and that load-balancing decisions are sta...
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Exact performance analysis of dynamic load-balancing policies for distributed systems is known to be very difficult owing to the facts that the state space is multidimensional and that load-balancing decisions are state dependent. In this paper, a state-aggregation method is proposed to model and analyze dynamic load-balancing policies. Those states with the same number of jobs are aggregated into a single state. The number of jobs in the system is modelled by a birth-death Markov process. The state transition rates are estimated by an iterative procedure. The procedure is developed according to the operation of the load-balancing policy. The proposed method is used to analyze the performance of a dynamic load-balancing policy, namely, symmetric policy. Extensive simulations are performed to study the accuracy of the method. This method provides accurate performance estimates for the symmetric policy for systems of various sizes when the mean job transfer delay is small compared to the average job service time.
In this paper, we present the IRIS architectural synthesis system for high-performance digital signal processing. This tool allows non-specialists to automatically derive VLSI circuit architectures from high-level, al...
In this paper, we present the IRIS architectural synthesis system for high-performance digital signal processing. This tool allows non-specialists to automatically derive VLSI circuit architectures from high-level, algorithmic representations, and provides a quick route to silicon implementation. By incorporating anovel synthesis methodology, called the Modular Design Procedure, within the IRIS system, parameterised models of complex and innovative DSP hardware can be derived and automatically assembled to create new DSP systems. The nature of this synthesis methodology is such that designers can explore a large range of architectural alternatives, whilst considering all the architectural implications of using specific hardware to realise the circuit. The applicability of IRIS is demonstrated using the design examples of a second order Infinite Impulse Response filter and a one-dimensional Discrete Cosine Transform circuit.
We propose a minimax technique to extract the optimum grid structure that will minimize the error in the interpolation of multidimensional functions using sequential linear interpolation (SLI). The error criterion we ...
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We propose a minimax technique to extract the optimum grid structure that will minimize the error in the interpolation of multidimensional functions using sequential linear interpolation (SLI). The error criterion we use is the maximum absolute error. We apply this method to the problem of color printer characterization.
The ferromagnetic pole pieces of permanent magnet assembly for magnetic resonance imaging is optimally designed taking account of the pulse excited gradient coil field. In the design, the transient design sensitivity ...
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The ferromagnetic pole pieces of permanent magnet assembly for magnetic resonance imaging is optimally designed taking account of the pulse excited gradient coil field. In the design, the transient design sensitivity analysis is combined with the three-dimensional finite element method to give a search direction. The effects of the eddy currents, induced on the ferromagnetic pole pieces, on the main magnetic-field strength and homogeneity in diameter of interested region are also investigated.
A type of quasi-cyclic binary low-density parity-check (LDPC) codes based on array codes, which have low encoding complexity and good performance, are considered for use in magnetic recording channels. Their error cor...
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A type of quasi-cyclic binary low-density parity-check (LDPC) codes based on array codes, which have low encoding complexity and good performance, are considered for use in magnetic recording channels. Their error correction capability, for both elec.ronic and media noise, and more importantly, for erasures, is investigated using simulations. Compared with random binary and q-ary LDPC codes, these codes offer a good tradeoff between performance and complexity.
Micromachined inductors with submillimeter profiles and comparable elec.rical performance to thicker, commercially-available surface-mount devices, have been fabricated and characterized for low-megahertz dc-dc conver...
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Micromachined inductors with submillimeter profiles and comparable elec.rical performance to thicker, commercially-available surface-mount devices, have been fabricated and characterized for low-megahertz dc-dc converters. The fabrication approach involves micron-scale lamination of Ni/Fe cores, combined with three-dimensional micromachined copper windings. The magnetic core of the fabricated inductor has 72 laminations of 1-μm-thick Ni/Fe films. The inductor dimension is 11.5 × 5.7 × 0.7 mm, and the dc resistance is 150 mΩ. A maximum Q of 9.2 at 3 MHz with an inductance value of 2.3 μH and a dc saturation current (I80) of 0.2 A were obtained. Use of this inductor in a regulated dc-dc boost converter circuit (7-12 V) operating at 2.2 MHz yielded 1.9-W power output at 71% efficiency.
Hybrid conductive-permeable elec.romagnetic shields are a key passive approach in the mitigation of undesired alternating magnetic fields. An efficient design presented in this paper is a combination of variable perme...
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Hybrid conductive-permeable elec.romagnetic shields are a key passive approach in the mitigation of undesired alternating magnetic fields. An efficient design presented in this paper is a combination of variable permeable belts and a thin conductive nonmagnetic pipe. The shield is capable of satisfying severe performance criteria, in terms of shielding factor, weight, and cost, while providing adaptive tuning for an individual inducing source inside the shield. The potential for the shield is discussed using an extended qualitative and quantitative analysis of the experimental results obtained at a magnetic test facility and shown to be promising.
Microelec.romechanical systems (MEMS) technology can be utilized for the fabrication of magnetic structures in multiple frequency ranges, ranging from low-megahertz metal-core devices for dc-dc converters to high-freq...
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Microelec.romechanical systems (MEMS) technology can be utilized for the fabrication of magnetic structures in multiple frequency ranges, ranging from low-megahertz metal-core devices for dc-dc converters to high-frequency dielec.ric or air core devices for RF application. These devices can also be fabricated in multiple locations: integral with silicon chips, in the interconnect layer between chip and board, and directly on the printed wiring board, in order to yield ultracompact magnetic microsystems. This paper describes examples of each of these fabrication approaches: high-frequency dielec.ric-core inductors for CMOS power amplifiers integrated on-chip, high-frequency air-core inductors fabricated within the interconnect layer between chip and board, and low-frequency metal-core inductors for dc-dc power conversion.
Ultralow (0.4 mm) profile spiral inductors with multilayer micrometer-scale NiFe laminated cores were developed for compact-packaging power applications. A simple sacrificial Cu etching process was used to realize sev...
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Ultralow (0.4 mm) profile spiral inductors with multilayer micrometer-scale NiFe laminated cores were developed for compact-packaging power applications. A simple sacrificial Cu etching process was used to realize seven layers of 1.8-μm-thick laminations, forming the magnetic cores. The laminated cores were combined with a spiral coil to fabricate the spiral inductor in a hybrid fashion. The dimension of a complete device is 40 × 15 mm. In situ elec.rical characterization verified compatibility with compact-packaging applications. The inductor was implemented in a boost converter (5-10 V) operating at 2.2 MHz, which demonstrated 2-W output with overall efficiency exceeding 70%.
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