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Proceedings - 2004 International Conference on Parallel Processing, ICPP 2004

作者： Ali, Shoukat Maciejewski, Anthony A. Siegel, Howard Jay Kim, Jong-Kook University of Missouri-Rolla Dept. of Electrical Engineering Rolla MO 65409-0040 United States Colorado State University Dept. of Electrical Engineering Fort Collins CO 80523-1373 United States Colorado State University Dept. of Computer Science Fort Collins CO 80523-1373 United States Purdue University Sch. of Elec. and Comp. Engineering West Lafayette IN 47907-1285 United States

This research investigates two distinct issues related to a resource allocation: its robustness and the failure rate of the heuristic used to determine the allocation. The target system consists of a number of sensors feeding a set of heterogeneous applications continuously executing on a set of heterogeneous machines connected together by high-speed heterogeneous links. There are a number of quality of service (QoS) constraints that must be satisfied. A heuristic failure occurs if the heuristic cannot find an allocation that allows the system to meet its QoS constraints. The system is expected to operate in an uncertain environment where the workload, i.e., the load presented by the set of sensors, is likely to change unpredictably, possibly invalidating a resource allocation that was based on the initial workload estimate. The focus of this paper is the design of a static heuristic that: (a) determines a robust resource allocation, i.e., a resource allocation that maximizes the allowable increase in workload until a run-time reallocation of resources is required to avoid a QoS violation, and (b) has a very low failure rate. This study proposes a heuristic that performs well with respect to the failure rates and robustness to unpredictable workload increases. This heuristic is, therefore, very desirable for systems where low failure rates can be a critical requirement and where unpredictable circumstances can lead to unknown increases in the system workload.

关键词： Robustness (control systems)

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Flows in micro fluidic networks: From theory to experiment

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Natural Computing 2004年第4期3卷 395-410页

作者： Van Noort, Danny McCaskill, John S. Dept. of Ecol./Evolutionary Biology Princeton University Princeton NJ 08544 Guyot Hall United States Sch. of Computer Science/Engineering Seoul National University Sinlim-dong Seoul 151-742 San 56-1 South Korea Biomolecular Information Processing Ruhr-Universität Bochum Fraunhofer Inst. Zentrum Schloss D-53754 Sankt Augustin Germany

When complex flow structures are designed, such as in DNA computing, it is essential to be able to predict the flow pattern of the solutions in the fluidic network. A model based on the resistance of the channels and flow velocities of the inlets can eliminated re-iterative design steps. We have constructed a symbolic model using Mathematica® to determine the desired flow pattern based on the equations of Ohm and Kirchoff. The values from this simulation were used in a flow simulation program and then tested in a microflow network. Results show that the simulation and calculation match very well, while the experiments in the fluidic network show a flow pattern as predicted by the model. © 2004 Kluwer Academic Publishers.

关键词： DNA computing DNA selection Flow simulations Microfluidics Microtechnolgy

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Implementation of a testing environment for digital IP cores

Implementation of a testing environment for digital IP cores

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Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04

作者： Das, Sunil R. Jin, Chuan Jin, Liwu Assaf, Mansour H. Petriu, Emil M. Jone, Wen-Ben Sahinoglu, Mehmet Sch. of Info. Technol. and Eng. Fac. of Eng. University of Ottawa Ottawa Ont. K1N 6N5 Canada Department of Electrical Engineering University of Cincinnati Cincinnati OH 45221 United States Department of Computer Science Troy State University Montgomery Montgomery AL 36103 United States

ISBN: (纸本)078038248X

The subject paper proposes a Verilog HDL-based fault simulation and testing environment for embedded IP cores-based digital systems, specifically targeted towards synchronous memory-based systems, for detecting single stuck-line faults. The simulator emulates a typical BIST (built-in self-testing) environment with test pattern generator that sends its outputs to an MUT (module under test) and the output streams from the MUT are fed into a response data analyzer. A fault is detected if the module response is different from that of the fault-free module. All of the faults detected are recorded in a detailed simulation results file. The fault simulator is suitable for testing sequential circuits described in Verilog HDL. The automatic fault simulator generates tests for the MUT described at the gate and flip-flop level. There are very few constraints on the circuit. The simulation process is completely automatic, and requires no intervention from the designer during the test generation process. The paper describes in detail the architecture and applications of the fault simulator along with the models of sequential elements used. Results on some simulation experiments on ISCAS 89 sequential benchmark circuits are also provided.

关键词： Digital integrated circuits

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On the duality of constrained estimation and control

On the duality of constrained estimation and control

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American Control Conference (ACC)

作者： Goodwim GC J.A. De Dona M.M. Seron X.W. Zhuo Sch. of Electr. Eng. & Comput. Sci. Newcastle Univ. Callaghan NSW Australia School of Electrical Engineering and Computer Science The University of Newcastle Callaghan NSW Australia

We establish that the Lagrangian dual of a constrained linear estimation problem is a particular nonlinear optimal control problem. The result has an elegant symmetry, which is revealed when the constrained estimation... 详细信息

关键词： Lagrangian functions Constraint optimization State estimation Gaussian distribution Optimal control Symmetric matrices computer science Australia Kalman filters Linear systems

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Simplified ML detection sch.me for MIMO systems

Simplified ML detection scheme for MIMO systems

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IEEE Conference on Vehicular Technology (VTC)

作者： Jee Woong Kang Kwang Bok Ed School of Electrical Engineering & Computer Science Seoul National University Seoul Korea Sch. of Electr. Eng. Comput. Sci. Seoul Nat. Univ. South Korea

ISBN: (纸本)0780382552

We propose a simplified maximum likelihood (ML) detection sch.me, based on a multi-stage likelihood test, for MIMO systems. The proposed sch.me chooses several surviving symbol combinations at each stage by likelihood tests for the restricted sub-streams, feeds them to the next stage, and finally detects whole sub-streams at the last stage. According to simulation results, the proposed sch.me can achieve almost the same performance as that of the ML detection sch.me, with far less complexity.

关键词： MIMO Interference cancellation Transmitting antennas Maximum likelihood detection Receiving antennas Computational complexity computer science System testing Feeds Detectors

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Equatorial spread F irregularity characteristics over São Luís, Brazil, using VHF radar and GPS scintillation techniques

Equatorial spread F irregularity characteristics over São L...

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作者： Rodrigues, F.S. De Paula, E.R. Abdu, M.A. Jardim, A.C. Iyer, K.N. Kintner, P.M. Hysell, D.L. Inst. Nac. de Pesq. Espaciais DAE S. Jose dos Campos Sao Paulo Brazil Department of Earth Science Cornell University Ithaca NY United States Department of Physics Saurashtra University Rajkot-Gujarat India Sch. of Elec./Computer Engineering Cornell University Ithaca NY United States Aeronomy Division Inst. Natl. de Pesquisas Espaciais Av. dos Astronautas 1758 CP 515 Sao Jose dos Campos-SP Brazil Earth Science Department Cornell University 2108 Snee Hall Ithaca NY 14853-3801 United States India Sch. of Elec./Computer Engineering Cornell University 302 Rhodes Hall Ithaca NY 14853-3801 United States Earth Science Department Cornell University 2122 Snee Hall Ithaca NY 14853 United States

Multitechnique observations may considerably improve our understanding of factors responsible for the generation, growth, and dynamics of the destabilized nighttime equatorial F region plasma irregularities. In order to investigate the dynamics of plasma density irregularities of different scale sizes, a campaign of observations was conducted during 11-20 November 2001 at the Brazilian magnetic equatorial station São Luís (2.57°S, 44.21°W, dip latitude 1.73°S). We carried out observations using VHF coherent backscatter radar, two spaced GPS-based scintillation monitors, and one digisonde. Range type spread F on ionograms and radar plume signatures on range-time-intensity maps of the VHF radar started at similar times. In order to compare GPS L1 (1.575 GHz) scintillations and radar plumes we used the scintillation S4 index computed for the signal transmitted by the highest elevation satellite. GPS scintillations were not observed during the initial bottom-type layer shown by the radar;however, stronger scintillations (higher S4 values) were observed concurrently to stronger radar echoes. Although the time duration of GPS scintillation is longer than the duration of the plumes observed by the radar, ionosonde spread F is still much longer than scintillation occurrence, confirming that smaller scale-size irregularities decay faster. Zonal and vertical velocities of 5-m irregularities measured by the radar were analyzed jointly with the apparent zonal velocity of ∼400-m irregularities measured by the spaced-receiver scintillation method. Larger values of the zonal velocity measured by the scintillation technique were found during the explosive growth phase of radar plumes associated with large values of vertical drifts measured by the radar.

关键词： Global positioning system

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A new approach to reducing output ripple in switched-capacitor-based step-down DC-DC converters

A new approach to reducing output ripple in switched-capacit...

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Conference Record of the IEEE Industry Applications Society Annual Meeting (IAS)

作者： Jifeng Han A. von Jouane G.C. Temes School of Electrical Engineering and Computer Science Oregon State University Corvallis OR USA Oregon State University Corvallis OR US Sch. of Electr. Eng. & Comput. Sci. Oregon State Univ. Corvallis OR USA

Rapidly dropping power supply voltages and tight voltage regulation requirements for integrated circuits challenge power supply designers. A novel interleaved disch.rging (ID) approach is presented to reduce the output ripple in step-down switched-capacitor (SC) DC-DC converters. Simulation and experimental results of a four-stage SC DC-DC converter show that the TD approach can reduce the output ripple by a factor of three. The proposed ID approach also improves the converter efficiency by 7%. The ID approach is suitable for all step-down SC DC-DC converters and provides flexibility in design optimization.

关键词： DC-DC power converters Switching converters Voltage Power supplies Interleaved codes Capacitors Costs Application software Switching circuits computer science

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On robust ∞ filter design for uncertain neural systems: LMI optimization approach

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Applied Mathematics and Computation (New York) 2004年第3期159卷 625-639页

作者： Park, Ju H. Kwon, O. Lee, S. Won, S. Sch. of Elec. Eng./Computer Science Yeungnam University 214-1 Dae-Dong Kyongsan 712-749 Korea Republic of Department of Electrical Engineering Pohang Univ. of Sci. and Technology San 31 Hyoja-dong Pohang 790-784 Korea Republic of

This article deals with the robust ∞ filtering problem for neutral delay differential systems with parametric uncertainties. A linear matrix inequality (LMI) approach is proposed to design the robust ∞ filter such that the filtering system remains asymptotically stable and the bound of ∞ norm is minimized. The Lyapunov stability theory is used for analysis of the system. A numerical example is provided to illustrate the validity of proposed design approach. © 2003 Elsevier Inc. All rights reserved.

关键词： Robustness (control systems)

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Effect of wafer level packaging, silicon substrate and board material on gigabit board-silicon-board data transmission

Effect of wafer level packaging, silicon substrate and board...

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Electronic Components and Technology Conference (ECTC)

作者： W. Kim R. Madhavan J. Mao J. Choi S. Choi D. Ravi V. Sundaram S. Sankararaman P. Gupta Z. Zhang G. Lo M. Swaminathan R. Tummala S. Sitaraman C.P. Wong M. Iyer M. Rotaru A. Tay School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA US Sch. of Electr. & Comput. Eng. Georgia Inst. of Technol. Atlanta GA USA School of Electrical and Computer Engineering KAIST South Korea School of Materials Science and Engineering Georgia Institute of Technology Atlanta GA USA School of Materials Science and Engineering School of Mechanical Engineering Packaging Research Center Institute of Microelectronics Atlanta GA Singapore National University of Singapore Singapore

This paper discusses the effect of wafer level packaging, silicon substrate, and board material on gigabit data transmission. A test vehicle consisting of a co-planar silicon transmission line, two board transmission lines and wafer level packaging was used for evaluation. A silicon substrate with 100 /spl Omega/-cm resistivity was compared with a silicon substrate with 2000 /spl Omega/-cm resistivity to investigate the effect of silicon substrate on gigabit data transmission. For board transmission lines, six board materials such as Ciba thin film, Vialux from Dupont, FR4, Hitachi MCL-LX67, Nelco N4000-12, and APPE were compared to investigate the effect of board material. For wafer-level packaging, solder bumps with 50 /spl mu/m diameter and 100 /spl mu/m pitch were used, and the effect of parasitic capacitance in the solder bumps on gigabit data transmission was investigated. For the accurate simulation of the test vehicle in the time domain, a TDR characterization method and non-physical RLGC models for lossy transmission lines were used to characterize board and silicon transmission lines. This paper shows that better signal integrity in the test vehicle cannot be achieved only by using lower loss material, but also requires low parasitic capacitance for gigabit data transmission.

关键词： Wafer scale integration Silicon Data communication Substrates Vehicles Coplanar transmission lines Testing Conductivity Parasitic capacitance Propagation losses

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Spatial, temporal and spatio-temporal databases - Hot issues and directions for PhD research

Spatial, temporal and spatio-temporal databases - Hot issues...

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作者： Roddick, John F. Egenhofer, Max J. Hoel, Erik Papadias, Dimitris Salzberg, Betty Sch. of Informatics and Engineering Flinders University GPO Box 2100 Adelaide SA 5001 Natl. Ctr. for Geogr. Info./Analysis University of Maine Orono ME 04469-5711 United States Research and Development Environ. Systems Research Institute 380 New York Street Redlands CA 92373 United States Department of Computer Science Hong Kong Univ. of Sci./Technology Clearwater Bay Hong Kong Hong Kong Coll. of Comp./Information Science Northeastern University Boston MA 02115 United States

Spatial and temporal database systems, both in theory and in practice, have developed dramatically over the past two decades to the point where usable commercial systems, underpinned by a robust theoretical foundation, are now starting to appear. While much remains to be done, topics for research must be chosen carefully to avoid embarking on impractical or unprofitable areas. This is particularly true for doctoral research where the candidate must build a tangible contribution in a relatively short time. The panel session at the Eighth International Symposium on Spatial and Temporal Databases (SSTD 2003) held on Santorini Island, Greece [7] in July 2003 thus took as its focus the question What to focus on (and what to avoid) in Spatial and Temporal Databases : recommendations for doctoral research. This short paper, authored by the panel members, summarizes these discussions.

关键词： Database systems

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