This paper presents a novel 3D integration approach for system-on-package (SOP) based solutions for wireless communication applications. This concept has been applied for the 3D integration of a C band Wireless LAN (W...
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This paper presents a novel 3D integration approach for system-on-package (SOP) based solutions for wireless communication applications. This concept has been applied for the 3D integration of a C band Wireless LAN (WLAN) RF front-end module by means of stacking LTCC substrates using /spl mu/BGA technology. Characterization and modeling of RF vertical board-to-board transition, using /spl mu/BGA process are presented for the first time. Specific investigations for 5.8 GHz WLAN applications such as high performance embedded band-pass filter design, and a via-fed stacked cavity-backed patch antenna development are reported. GaAs MESFET-based Rx and Tx chipset is implemented in GaAs MESFET process and combined with the suggested package structure, demonstrating 3D integration concept suitable for C-band wireless communication applications.
1bit full adders and counters are usually used as basic cells in the arithmetic circuits. Characteristics of these components have strong impact on power, delay, and area of the arithmetic circuits. In this paper we p...
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ISBN:
(纸本)9780769514413
1bit full adders and counters are usually used as basic cells in the arithmetic circuits. Characteristics of these components have strong impact on power, delay, and area of the arithmetic circuits. In this paper we propose a design method for low power arithmetic circuits, which the designer selects basic cells from a set of circuits with different structures(symmetrical one and asymmetrical one) by the method and the mothod optimizes connections to the terminals of the basic cells. Experimental results demonstrate 32.1% power reduction of a parallel multiplier designed by the proposed technique.
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit design. This paper proposes a new desi...
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ISBN:
(纸本)0769514413
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit design. This paper proposes a new design method, in which basic cells are selected from a set of circuits with different structures (symmetrical and asymmetrical) and connections to their terminals are exchanged, according to input-patterns to minimize power consumption. Experimental results for a parallel multiplier demonstrate average 30% power reduction.
This paper presents design and analysis of a rigid link finger, which may be suitable for a number of adaptive end effectors. The design has evolved from an industrial need for a tele-operated system to be used in nuc...
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We propose a novel harmonic boosting technique for development of high performance subharmonic mixers. This technique alleviates major problems associated with the use of 4/sup th/ and higher order subharmonic mixers....
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We propose a novel harmonic boosting technique for development of high performance subharmonic mixers. This technique alleviates major problems associated with the use of 4/sup th/ and higher order subharmonic mixers. By utilizing the odd-order harmonics of the main subharmonic LO, we demonstrate significant performance improvements while reducing the LO power. Measurements confirm a 6 dB savings in LO power level, up to 10 dB improvement in output P1dB and up to 6 dB improvement in conversion loss. Measurements also confirm that harmonic boosting does not degrade in-band LO leakage, IIP2 and dc offset levels, thus favoring its application in very-low-IF and direct conversion transceivers.
This paper presents design and analysis of a rigid link finger, which may be suitable for a number of adaptive end effectors. The design has evolved from an industrial need for a tele-operated system to be used in nuc...
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In this paper, CMOS RF down-conversion mixer circuit hot-carrier (HC) and soft breakdown (SBD) reliability estimation and redesign is presented. First of all, MOS transistor reliability under analog operation was eval...
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In this paper, CMOS RF down-conversion mixer circuit hot-carrier (HC) and soft breakdown (SBD) reliability estimation and redesign is presented. First of all, MOS transistor reliability under analog operation was evaluated by experiment. The mixer circuit operation conditions for the occurrence of HC and SBD are analyzed, and circuit performance model are presented to relate the device degradation to circuit performance degradation. Finally, we propose mixer circuit redesign strategies, which reduce the HC and SBD problem. Simulation shows improved noise performance with the similar gain, IIP3 and power consumption.
Front grid pattern of standard crystalline solar cells is specifically designed for screen printed silver paste contact. A detailed theoretical analysis of the proposed segmented cross grid line pattern has been carri...
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Front grid pattern of standard crystalline solar cells is specifically designed for screen printed silver paste contact. A detailed theoretical analysis of the proposed segmented cross grid line pattern has been carried out for optimizing the spacing and widths of the grid finger, main and sub-bus bars. It is shown that by choosing properly the grid pattern and optimizing the grid parameter, the overall front contact electrical and optical losses can be brought down to 10% or less as compared to the usual loss of 15% or more obtained with the conventional screen printed silver paste technology. Limitation of conventional screen printed contact has been pointed out. It was also observed that the total normalized power loss for segmented mesh grid with plated metal contact, the total power loss can be brought down to 10.04 percent unlike 11.57 for the case of continuous grid and plated contact.
In this paper, CMOS RF down-conversion mixer circuit hot-carrier (HC) and soft breakdown (SBD) reliability estimation and redesign is presented. First of all, MOS transistor reliability under analog operation was eval...
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In this paper, CMOS RF down-conversion mixer circuit hot-carrier (HC) and soft breakdown (SBD) reliability estimation and redesign is presented. First of all, MOS transistor reliability under analog operation was evaluated by experiment. The mixer circuit operation conditions for the occurrence of HC and SBD are analyzed, and a circuit performance model is presented to relate device degradation to circuit performance degradation. Finally, we propose mixer circuit redesign strategies, which reduce the HC and SBD problem. Simulation shows improved noise performance with similar gain, IIP3 and power consumption.
We present C-band oscillators with external high-Q inductors: wire-bond inductors and embedded inductors in a Multi-Layer Organic (MLO) board fabricated by a thick-film MCM-L technology. The phase-noise performance of...
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We present C-band oscillators with external high-Q inductors: wire-bond inductors and embedded inductors in a Multi-Layer Organic (MLO) board fabricated by a thick-film MCM-L technology. The phase-noise performance of oscillators is compared with the oscillator using on-chip inductors. Inductors are designed to obtain high quality factor in C-band. The phase-noise performance of the oscillator with on-chip inductors measures -108 dBc/Hz at 600 kHz offset frequency, and that of the oscillator with external inductors shows -113 dBc/Hz at the same offset. Using MLO inductors, the phase-noise is better than the oscillator with on-chip inductors and comparable to the oscillator with wire-bond inductors. To our knowledge, this is the first C-band oscillator using inductors embedded in the multi-layer organic packaging technology. This is also the first report comparing the performance of oscillators using three different inductor technologies: on-chip integration, wire-bonding, and multi-layer organic packaging technology.
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