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Research and Educational Experiment Workshop (GREE), GENI

作者： Ashkan Ghaffarinejad Violet R. Syrotiuk School of Computing Informatics and Decision Systems Engineering Arizona State University Tempe AZ

Today, commercial load balancers are often in use, including in the production network at Arizona State University (ASU). One of the main issues such load balancers face is that they use a static scheme for load distribution. However, at particular times of the academic year, such as during course registration, the network exhibits significant variations in both temporal and spatial traffic characteristics. At these times, students experience much greater latency and become frustrated with the network service. To address this problem, our aim is to develop an SDN-based approach to load balancing to better cope with the traffic variation.

关键词： Switches Load management Servers Software Educational institutions Computer architecture

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Integration of threshold logic gates with RRAM devices for energy efficient and robust operation 14

Integration of threshold logic gates with RRAM devices for e...

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IEEE International Symposium on Nanoscale Architectures (NANOARCH)

作者： Jinghua Yang Niranjan Kulkarni Shimeng Yu Sarma Vrudhula School of Computing Informatics and Decision Systems Engineering Arizona State University Tempe Arizona

ISBN: (纸本)9781450328340

Differential mode threshold-logic gates can be programmed to compute complex logic functions within a single cell, resulting in significant reduction in area and power. However the circuit yield reduces if they are operated at low voltages. This paper describes a novel integration of RRAM with such threshold-logic gates to achieve robust, low voltage (0.6V for 65nm technology) and energy efficient computation of threshold-logic functions. Below 0.6V, we observed that the performance(and thereby, energy delay product) of conventional CMOS circuits degrades substantially compared to the proposed threshold-logic circuits. The improvement in performance and energy of the new circuit architecture are demonstrated while considering process variations in both the MOSFET and RRAM devices. For each threshold function implementable by threshold-logic gate, comparison of energy, delay and energy delay product with equivalent CMOS implementation is given. The advantages in area, energy and delay of threshold logic implementations over conventional CMOS logic gates is demonstrated by two commonly used functional components.

关键词： Logic gates Transistors Resistance Computer architecture Delays Low voltage Resistors

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Attribute-based access control for ICN naming scheme

Attribute-based access control for ICN naming scheme

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IEEE Conference on Communications and Network Security (CNS)

作者： Bing Li Ashwin Prabhu Verleker Dijiang Huang Zhijie Wang Yan Zhu School of Computing Informatics and Decision Systems Engineering ASU USA School of Computer and Communication Engineering USTB China

Information Centric Networking (ICN) is a new network architecture that aims to overcome the weakness of existing IP-based networking architecture. Instead of establishing a connection between the communicating hosts, ICN focuses on the content, i.e. data, transmitted in network. Content copies in ICN can be cached at different locations. The content is out of the owner's control once it's published. Thus, enforcing access control policies on distributed content copies is crucial in ICN. Attribute-Based Encryption (ABE) is a feasible approach to enforce such control mechanisms. However, applying ABE in ICN has two challenges: from management perspective, managing attributes is complicated in distributed manners; from privacy perspective, unlike in traditional networks, the enforced content access policies are public to all the ICN users. Thus, it is desirable that unauthorized content viewers are not able to retrieve the access policy. To this end, a privacy-preserving access control scheme for ICN and associated attribute management solution are presented in this paper. This proposed approach is compatible with existing flat name based ICN architectures.

关键词： Access control Ontologies Magnetic resonance imaging Encryption Medical services

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Occupational Macroergonomics: Principles, Scope, Value, and Methods

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IIE transactions on occupational ergonomics and human factors 2015年第1期3卷 1-8页

作者： Richard J Holden A Joy Rivera Pascale Carayon Department of BioHealth Informatics School of Informatics and Computing Indiana University Walker Plaza - WK319 719 Indiana Avenue Indianapolis IN 46202 USA. Children's Hospital of Wisconsin Milwaukee Wisconsin USA. Department of Industrial and Systems Engineering University of Wisconsin-Madison Madison Wisconsin USA Center for Quality and Productivity Improvement University of Wisconsin-Madison Madison Wisconsin USA.

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Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture

Scaling and operation characteristics of HfOx based vertical...

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2014 IEEE International Symposium on Circuits and systems, ISCAS 2014

作者： Kang, J.F. Gao, B. Chen, B. Huang, P. Zhang, F.F. Liu, X.Y. Chen, H.-Y. Jiang, Z. Wong, H.-S. Philip Yu, Shimeng Institute of Microelectronics Peking University Beijing 100871 China Department of Electrical Engineering Stanford University Stanford CA 94305 United States School of Computing Informatics and Decision Systems Engineering Arizona State University AZ 85281 United States

ISBN: (纸本)9781479934324

Stacked HfOx based vertical RRAM with interface engineering for 3D cross-point architecture is fabricated using a cost-effective fabrication process. The excellent performances such as low reset current, fast switching speed, high switching endurance and disturbance immunity, good retention and self-selectivity are demonstrated in the fabricated HfOx based vertical RRAM devices. The scaling limit and the functionality along with a viable write/read scheme of the presented vertical RRAM are investigated. The experiments show that the pillar electrode thickness and the plane electrode thickness of the vertical RRAM can be scaled down to 3nm and 5nm without significant performance degradation, respectively. © 2014 IEEE.

关键词： Cost effectiveness

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Multi-tenancy and Sub-tenancy Architecture in Software-as-a-Service (SaaS)

Multi-tenancy and Sub-tenancy Architecture in Software-as-a-...

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2014 IEEE 8th International Symposium on Service Oriented System engineering

作者： Wei-Tek Tsai Peide Zhong School of Computing Informatics and Decision Systems Engineering Arizona State University Tempe AZ USA

Multi-tenancy architecture (MTA) is often used in Software-as-a-Service (SaaS) and the central idea is that multiple tenant applications can be developed using components stored in the SaaS infrastructure. Recently, MTA has been extended where a tenant application can have its own sub-tenants as the tenant application acts like a SaaS infrastructure. In other words, MTA is extended to STA (Sub-Tenancy Architecture). In STA, each tenant application not only needs to develop its own functionalities, but also needs to prepare an infrastructure to allow its sub-tenants to develop customized applications. This paper formulates eight models for STA, and discusses their trade-offs including their formal notations and application scenarios.

关键词： Software as a service Data models Organizations Databases Computer architecture Scalability Security

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On shortest single/multiple path computation problems in Fiber-Wireless (FiWi) access networks

On shortest single/multiple path computation problems in Fib...

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IEEE Workshop on High Performance Switching and Routing

作者： Chenyang Zhou Anisha Mazumder Arunabha Sen Martin Reisslein Andrea Richa Informatics and Decision Systems Engineering School of Comoputing

Fiber-Wireless (FiWi) networks have received considerable attention in the research community in the last few years as they offer an attractive way of integrating optical and wireless technology. As in every other type of networks, routing plays a major role in FiWi networks. Accordingly, a number of routing algorithms for FiWi networks have been proposed. Most of the routing algorithms attempt to find the “shortest path” from the source to the destination. A recent paper proposed a novel path length metric, where the contribution of a link towards path length computation depends not only on that link but also every other link that constitutes the path from the source to the destination. In this paper we address the problem of computing the shortest path using this path length metric. Moreover, we consider a variation of the metric and also provide an algorithm to compute the shortest path using this variation. As multipath routing provides a number of advantages over single path routing, we consider disjoint path routing with the new path length metric. We show that while the single path computation problem can be solved in polynomial time in both the cases, the disjoint path computation problem is NP-complete. We provide optimal solution for the NP-complete problem using integer linear programming and also provide two approximation algorithms with a performance bound of 4 and 2 respectively. The experimental evaluation of the approximation algorithms produced a near optimal solution in a fraction of a second.

关键词： Measurement Routing Approximation algorithms Approximation methods Optical fiber networks Polynomials Wireless communication

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Refining Traffic Information for Analysis Using Evidence Theory

Refining Traffic Information for Analysis Using Evidence The...

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MILCOM, Military Communications Conference

作者： Bing Li Dijiang Huang Zhijie Wang School of Computing Informatics and Decision Systems Engineering Arizona State University Tempe AZ USA

ISBN: (纸本)9781479967711

Anonymous communication is important and desirable in a wide range of networking systems to guarantee secure and private communications. This feature is especially important in mobile ad hoc networks (MANETs) where the communication channel is publicly open and the sessions are vulnerable to passive attacks. The fact that MANETs are mostly used in crucial environments such as military usage and disaster rescue emphasizes this importance. In our previous work [1], [2], a theoretic approach and its evaluation methods were developed to model the anonymity performance. The corresponding methods for handling localization errors and scalability issues were also proposed. However, an effective approach to handle the fuzzy information acquired from the network needs to be further developed. To this end, we develop a comprehensive evidence based method to handle the information that a monitoring system can acquire in realistic model and the corresponding analysis approach to process the various evidences from multiple sources. The purpose of this work is to evaluate how much information regarding the anonymous communication is leaked into the wireless channel. The evaluation of the proposed method shows a satisfactory performance in terms of accuracy in reconstructing the anonymous communication patterns in real-world scenarios.

关键词： Monitoring Ad hoc networks Mobile computing Sensor systems Mobile nodes

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ReMAP: Reuse and memory access cost aware eviction policy for last level cache management

ReMAP: Reuse and memory access cost aware eviction policy fo...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Akhil Arunkumar Carole-Jean Wu School of Computing Informatics and Decision Systems Engineering Arizona State University Tempe AZ USA

To mitigate the significant main memory access latency in modern chip multiprocessors, multi-level on-chip caches are used to bridge the gap by retaining frequently used data closer to the processor cores. Such dependence on the last-level cache (LLC) has motivated numerous innovations in cache management schemes. However, most prior works focus their efforts on optimizing cache miss counts experienced by applications, irrespective of the interactions between the LLC and other components in the memory hierarchy such as the main memory. This results in sub-optimal performance improvements, since reducing miss rates does not directly translate to increased IPC performance. In this paper, we show that in addition to the recency information provided by the cache replacement policy, post eviction reuse distance (PERD) and main memory access latency cost are useful to make better-informed eviction decisions at the LLC. We propose ReMAP, Reuse and Memory Access Cost aware eviction policy, that takes reuse characteristics and memory access behavior into consideration when making eviction decisions. ReMAP achieves higher performance compared to prior works. Our full-system simulation results show that ReMAP reduces the number of misses of SPEC2006 applications by as much as 13% over the baseline LRU replacement and by an average of 6.5% while MLP-aware replacement and DRRIP reduce the miss counts by -0.7% and 5% respectively. More importantly, ReMAP achieves an average of 4.6% IPC performance gain across the SPEC2006 applications while MLP-aware replacement and DRRIP see only 1.8% and 2.3% respectively.

关键词： Benchmark testing Memory management Estimation Hardware Random access memory Radiation detectors Hidden Markov models

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CAWS: Criticality-aware warp scheduling for GPGPU workloads

CAWS: Criticality-aware warp scheduling for GPGPU workloads

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International Conference on Parallel Architecture and Compilation Techniques (PACT)

作者： Shin-Ying Lee Carole-Jean Wu Computer Science and Engineering School of Computing Informatics and Decision Systems Engineering Arizona State University Tempe AZ

ISBN: (纸本)9781509066070

The ability to perform fast context-switching and massive multi-threading is the forte of modern GPU architectures, which have emerged as an efficient alternative to traditional chip-multiprocessors for parallel workloads. One of the main benefits of such architecture is its latency-hiding capability. However, the efficacy of GPU's latency-hiding varies significantly across GPGPU applications. To investigate this, this paper first proposes a new algorithm that profiles execution behavior of GPGPU applications. We characterize latencies caused by various pipeline hazards, memory accesses, synchronization primitives, and the warp scheduler. Our results show that the current round-robin warp scheduler works well in overlapping various latency stalls with the execution of other available warps for only a few GPGPU applications. For other applications, there is an excessive latency stall that cannot be hidden by the scheduler effectively. With the latency characterization insight, we observe a significant execution time disparity for warps within the same thread block, which causes suboptimal performance, called the warp criticality problem. To tackle the warp criticality problem, we design a family of criticality-aware warp scheduling (CAWS) policies by scheduling the critical warp(s) more frequently than other warps. Our results on the breadth-first-search, B+tree search, two point angular correlation function, and K-means clustering show that, with oracle knowledge of warp criticality, our best-performing scheduling policy can improve GPGPU applications' performance by 17% on average. With our designed criticality predictor, the various scheduling policies can improve performance by 10-21% on breadth-first-search. To our knowledge, this is the first paper to characterize warp criticality and explore different criticality-aware warp scheduling policies for GPGPU workloads.

关键词： Graphics processing units Hazards Instruction sets Computer architecture Scheduling Pipelines Computational modeling

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