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IEE Colloquium on computer Image Processing and Plant Control

作者： J.A. Ware R.A. Davies G. Roberts J.H. Williams Department of Mathematics and Computing Polytechnic of Wales Pontypridd Mid-Glamorgan UK Department of Computer Studies Polytechnic of Wales Pontypridd Mid-Glamorgan UK School of Electrical Electronic and Systems Engineering University of Wales Cardiff UK

The manipulation of objects by a robot within its workspace requires knowledge about each object's location and orientation. A 3D representation of the robot's workspace is thus required. This 3D representation would be built up from information obtained from various sensors within the workspace. In the paper the sensors used are robot mountable CCD Cameras. In the transputer based system developed, the process of extracting the information from the cameras is separated from the processes that use this information. This separation of information provider from information user enables the software that controls the cameras (and even the cameras themselves) to be upgraded with no corresponding changes to the information user software. Additional cameras can easily be added to the system while obsolete cameras and those with poor imaging characteristics can simply be removed.< >

关键词： Charge coupled image sensors Machine vision Pattern recognition Image processing Industrial control Microprocessors

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Diagnosing CMOS bridging faults with stuck-at fault dictionaries

Diagnosing CMOS bridging faults with stuck-at fault dictiona...

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IEEE International Test Conference

作者： S.D. Millman E.J. McCluskey J.M. Acken Motorola Inc. Mesa AZ USA Center for Reliable Computing Computer Systems Laboratory Departments of Electrical Engineering and Computer Science University of Stanford Stanford CA USA Schlumberger Technologies Palo Alto CA USA Intel Corporation Santa Clara CA USA

It is shown that the traditional approach to diagnosing stuck-at faults with fault dictionaries generated for stuck-at faults is not appropriate for diagnosing CMOS bridging faults. A novel technique for using stuck-at-fault dictionaries to diagnose bridging faults is described. Teradyne's LASAR was used to simulate bridging and stuck-at faults in a number of combinational circuits, including parity trees, multiplexers, and the 74ASCI181 4-b, 16-function ALU (arithmetic and logic unit). When the traditional technique was used, between 30%-50% of the bridging faults were mis-diagnosed, with the presence of a failure indicated on a fault-free node. In addition, as the stuck-at-fault diagnostic ability of a test increased, the bridging fault diagnostic ability decreased. By use of the new technique. over 92% of the bridging faults in the circuits used for this research were diagnosed correctly and less than 4% led to misleading diagnoses.< >

关键词： Dictionaries Circuit faults Fault diagnosis Circuit testing Fault detection Laboratories Semiconductor device modeling CMOS technology Computational modeling Circuit simulation

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The critical path for multiple faults

The critical path for multiple faults

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IEEE International Conference on computer-Aided Design

作者： S. Makar E. McCluskey CENTER FOR RELIABLE COMPUTING Computer Systems Laboratory Depts. of Electrical Engineering and Computer Science University of Stanford CA USA

The critical path technique for determining the single stuck-at faults detected by a test is extended to multiple faults by defining masking paths. A masking tree is used to represent the masking relationships among individual faults. These relationships are then used to determine which multiple faults are actually detected by a test.< >

关键词： Circuit faults electrical fault detection Fault detection Circuit testing Circuit simulation Laboratories computer science System testing Very large scale integration Manufacturing

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A self-test and self-diagnosis architecture for boards using boundary scans

A self-test and self-diagnosis architecture for boards using...

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European Test Conference

作者： L.-T. Wang M. Marhoefer E.J. McCluskey CENTER FOR RELIABLE COMPUTING ERL 460 Computer Systems Laboratory Departments of Electrical Engineering and Computer Science University of Stanford Stanford CA USA ZFE F2 DES 233 Siemens AG Munchen Germany

The authors present a low-cost self-test and self-diagnosis architecture for locating both defective chips and bad interconnects on a printed-circuit board. It is assumed that the boundary scan method developed by the Joint Task Action Group (JTAG) is applied to all chips on the board. To achieve high fault coverage, the proposed method uses pseudorandom patterns from a cellular automaton to locate defective chips, and walking sequences to locate bad interconnects. It is shown that the effectiveness of this method depends on the type of circuits to be tested.< >

关键词： Built-in self-test System testing Automatic testing Hardware Logic testing computer architecture Laboratories Surface-mount technology Automata Legged locomotion

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Morphological based target enhancement algorithms to counter the hostile nuclear environment

Morphological based target enhancement algorithms to counter...

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IEEE International Conference on systems, Man and Cybernetics

作者： C.H.G. Wright E.J. Delp N.C. Gallagher HQ Space Systems Division Los Angeles Air Force Base Los Angeles CA USA Computer Vision and Image Processing Laboratory School of Electrical Engineering Purdue University West Lafayette IN USA

It is noted that a necessary requirement of a strategic defense system is the detection of incoming nuclear warheads in an environment that may include nuclear detonations of undetected or missed target warheads. A computer model is described which simulates incoming warheads as distant endoatmospheric targets. A model of the expected electromagnetic noise present in the nuclear environment is developed; predicted atmospheric effects are included. Various morphological-based image-enhancement algorithms are examined with regard to their ability to suppress the noise and atmospheric effects of the nuclear environment. These algorithms are then tested, using the combined target and noise models, and evaluated in terms of noise removal and the ability to resolve closely spaced targets.< >

关键词： Counting circuits Atmospheric modeling Working environment noise Nuclear weapons Computational modeling computer simulation Predictive models Electromagnetic modeling Electromagnetic interference Testing

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CIRCUITS FOR PSEUDOEXHAUSTIVE TEST PATTERN GENERATION

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IEEE TRANSACTIONS ON computer-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 1988年第10期7卷 1068-1080页

作者： WANG, LT MCCLUSKEY, EJ Center for Reliable Computing Computer Systems Laboratory Departments University of Stanford Stanford CA USA Center for Reliable Computing Computer Systems Laboratory Departments of Electrical Engineering and Computer Science University of Stanford Stanford CA USA

Implementation methods based on cyclic codes are presented for pseudoexhaustive testing of combinational logic networks with restricted output dependency. A modified linear-feedback shift register (LFSR) is used to generate exhaustive test patterns for every output of the circuit. All detectable, combinational faults (those that do not change a combinational circuit to a sequential circuit) in each cone of logic driving a single output are guaranteed to be detected. Examples indicate that LFSRs based on cyclic codes have lower hardware cost and shorter or comparable test lengths than other approaches. These test-pattern generators are well suited to applications where short testing time, low hardware overhead, and 100% single-stuck-at fault coverage are required.< >

关键词： Test pattern generators Circuit testing Logic testing electrical fault detection Fault detection Circuit faults Combinational circuits Sequential circuits Hardware Shift registers

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Logic design education at Stanford University

Logic design education at Stanford University

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： J.F. Wakerly E.J. McCluskey Center for Reliable Computing Computer Systems Laboratory Departments of Electrical Engineering and Computer Science University of Stanford Stanford CA USA

Recent developments in the logic design courses in the computer systems laboratory at Stanford University are described. The courses include an introductory undergraduate lecture and laboratory course, an advanced und... 详细信息

关键词： Logic design Laboratories CMOS logic circuits Combinational circuits Logic circuits Pulse inverters Sequential circuits Logic functions Logic devices CMOS technology

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OPTICAL SYMBOLIC computing

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Optics News 1988年第12期14卷 40-41页

作者： W. THOMAS CATHEY GARRET R. MODDEL RODNEY A. SCHMIDT OPTOELECTRONIC COMPUTING SYSTEMS CENTER AND DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING UNIVERSITY OF COLORADO BOULDER COLO. OPTOELECTRONIC COMPUTING SYSTEMS CENTER AND DEPARTMENT OF MATHEMATICS COLORADO SCHOOL OF MINES GOLDEN COLO.

No abstract available.

关键词： Laser beams Light intensity Liquid crystal devices Liquid crystal displays Optical components Solar radiation

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Concurrent Error Detection and Testing for Large PLA's

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IEEE Journal of Solid-State Circuits 1982年第2期17卷 386-394页

作者： Khakbaz, Javad McCluskey, Edward J. Center for Reliable Computing Computer Systems Laboratory Departments of Electrical Engineering and Computer Science Stanford University Stanford CA 94305 United States

A system of checkers is designed for concurrent error detection in large PLA's. This system combines concurrent error detection with off-line functional testing of the PLA by using the same checker hardware for both purposes. The result is a significant saving in hardware cost. For a case example, the total hardware cost is estimated at about 37 percent of the original PLA area. The system is almost totally self-checking and, although the test patterns are not function-independent, their generation algorithm is simple. The total test time for the entire system is within the range of that of some recent PLA design schemes which were specifically aimed at simplifying off-line testing, but which have no provisions for concurrent error detection. Copyright © 1982 by the Institute of electrical and Electronics Engineers, Inc.

关键词： Programmable logic arrays Circuit testing System testing Hardware Costs Fault detection Test pattern generators Logic arrays Logic testing Digital systems

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NAVAL COASTAL systems laboratory - UNIQUE INSITU TEST AND EVALUATION SITE

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NAVAL ENGINEERS JOURNAL 1978年第2期90卷 119-129页

作者： JOLLIFF, JV CALLAHAN, CM USN Capt. James V. Jolliff USNgraduated from the U. S. Naval Academy in 1954. Following graduation he served in the USS S. N. Moore (DD—747) and USS Cimarron (AO—22). He received his MS degrees in Naval Architecture from Webb Institute of Naval Architecture and in Financial Management from The George Washington University. He culminated his education at The Catholic University of America where he was awarded his Doctorate in Ocean Engineering in 1972. Capt. Jolliff has served in Naval Shipyards as Ship Superintendent Assistant Repair Officer and Assistant Planning & Estimating Superintendent and as such was primarily concerned with the repair and conversion of U. S. Navy skips. In addition he has served as Maintenance Officer Staff of Commander Mine Force U. S. Pacific Fleet as Co—Chairman of the Naval Engineering Division Engineering Department U. S. Naval Academy and as CV Design Manager in the Advanced Concepts Division and as Head Ship Survivability Office Naval Ship Engineering Center. An active member of ASNE since 1966 he has served as a member of the National Council and is currently the Chairman of the Journal Committee. He has had several papers presented at ASNE Day and published in the Journal and in 1976 was one of the recipients of the ASNE President's Award. At the present time he is assigned as the Commanding Officer Naval Coastal Systems Laboratory (NCSL) Panama City Fla. Mr. Casville M. Callahanis a native of Southwest Virginia where he attended Elementary and Secondary School prior to his three year's service in the U. S. Navy during World War II. He graduated from Lincoln Memorial University Harrogate Tenn. in 1950 receiving his BS degree in Mathematics. In 1952 he received his MS degree in Mathematics from Auburn University Auburn Ala. and taught mathematics at Lincoln Memorial University and at Florida State University Tallahassee Fla. prior to joining the staff of the Mine Defense Laboratory in 1955. He has progressed through a variety of assignments as the Labo

Test and Evaluation have become paramount in today's Department of Defense acquisition process. Therefore, the U. S. Navy requires both private and public facilities to accomplish the final goals of the “Fly before Buy” concept. Such a facility exists at the Naval Coastal systems laboratory (NCSL); an integral part of the Chief of Naval Material's, Director of Navy Laboratories organization. This paper briefly addresses the laboratory, its mission, and its history. This is followed by an in—depth facilities overview in order to create an understanding of the slow but steady evolution of NCSL's unique fixed facilities. These facilities, when coupled to the local natural environment, provide a unique in situ test and evaluation capability which is unequalled in the United States for assessing seagoing coastal systems. Of prime consideration is the Range Date Acquisition Center (RADAC) and Its ancillary subsystems for tracking, environmental monitoring, communications, and post run analysis. The paper is concluded with a discussion of both past and present use of the aforementioned facilities with an emphasis on user acceptance and future potential growth.

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