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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Dimitris Bekiaris George Economakos Efstathios Sotiriou-Xanthopoulos Dimitrios Soudris School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory National and Technical University of Athens Athens Greece

Reconfigurable computing is a cost-effective alternative to technology shrinking in order to achieve higher performance in digital design, especially considering run time reconfiguration. Research in the field consists of new reconfigurable architectures, either coarse-grain or fine-grain, and new methodologies to map applications onto them. A special case of coarse-grain reconfigurable components are morphable multipliers, which use multiplexers to feed different inputs and form different connection schemes within the data path of conventional multipliers. These connection schemes form different components that can be utilized when the initial multiplier is idle. Morphable components offer performance improvements but the use of extra multiplexers impose power overheads. This paper applies two low-power design techniques, power gating and multi V th components, for the design of low-power morphable multipliers. Experimentation with these multipliers in a high-level synthesis flow show that they can offer performance, area and power improvements compared to alternative architectures, making them valuable building blocks for hardware synthesis.

关键词： Multiplexing Adders computer architecture Hardware Timing Sparks microprocessors

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Performance analysis and complexity study of LDPC and turbo coding schemes for inter vehicle communications

Performance analysis and complexity study of LDPC and turbo ...

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International Conference on ITS Telecommunications (ITST)

作者： George Kiokes George Economakos Angelos Amditis Nikolaos K. Uzunoglu Institute of Communication and Computer Systems (ICCS) I-SENSE Group National Technical University of Athens Greece School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory National Technical University of Athens Greece School of Electrical and Computer Engineering Microwaves and Optics Laboratory National Technical University of Athens Greece

This paper provides a comprehensive investigation of the performance and practical implementation issues of two coding schemes, employing Turbo Codes and low-density parity-check (LDPC) codes, over vehicular ad-hoc networks based on IEEE 802.11p specifications. Using simulation authors present the results of an evaluation of system performance for the two different coding schemes. We concentrate our evaluation on two different environments AWGN and Non Line of Sight propagation environment (Rayleigh Fading). BER (Bit Error Rate) and SNR (Signal to Noise Ratio) values for QPSK modulation are examined and tested. The Forward Error Correction (FEC) system model in the transceiver with the two schemes has been implemented in a Field Programmable Gate Array (FPGA) from Xilinx. At the end, a test-bed was developed using the Nallatech XtremeDsp Development Kit with a Xilinx Virtex-4 FPGA, for comparing simulation results with real time implementations.

关键词： Iterative decoding Decoding Turbo codes Field programmable gate arrays

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FPGA implementation of a pipelined 2D-DCT and simplified quantization for real-time applications

FPGA implementation of a pipelined 2D-DCT and simplified qua...

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2011 International Conference on Multimedia Computing and systems, ICMCS'11

作者： Anas, Hatim Belkouch, Said El Aakif, M. Chabini, Noureddine Embedded Systems and Digital Control Laboratory National School of Applied Sciences University of Cadi Ayyad Av. Abdelkarim Khattabi Guéliz Marrakech Morocco Department of Electrical and Computer Engineering Royal Military College of Canada Kingston ON Canada

ISBN: (纸本)9781612847306

The Discrete Cosine Transform (DCT) is one of the most widely used techniques for image compression. Several algorithms are proposed to implement the DCT-2D. The scaled SDCT algorithm is an optimization of the DCT-1D, which consists in gathering all the multiplications at the end. In this paper, in addition to the hardware implementation on an FPGA, an extended optimization has been performed by merging the multiplications in the quantization block without having an impact on the image quality. Tests using MATLAB environment have shown that our proposed approach produces images with quality comparable to the ones obtained using the JPEG standard. FPGA-based implementations of this proposed approach and the Loeffler's algorithm are proposed and compared in this paper using an Altera Startix FPGA family with the synthesis and implementation tool Quartus II. Results show that our approach outperforms the well known Loeffler's algorithm in terms of processing-speed and resources used. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A Reconfigurable IP Characterization Technique Improving High-Level Synthesis Results

A Reconfigurable IP Characterization Technique Improving Hig...

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International Conference on Design & Technology of Integrated systems in Nanoscale Era

作者： Efstathios Sotiriou-Xanthopoulos Ioannis Koutras George Economakos Dimitrios Soudris National Technical University of Athens School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory

ISBN: (纸本)9781612848990

Reconfigurable computing is a cost-effective alternative to technology shrinking in order to achieve higher performance in digital design, especially considering run time reconfiguration. Research in the field consists of new reconfigurable architectures, either coarse-grain or fine-grain, and new methodologies to map applications onto them. Usually, top-down methodologies are proposed, that start from the application's dataflow graph and try to merge different parts into the same reconfigurable component. This paper presents a bottom-up approach, that searches available RTL component libraries for primitives that can be connected in alternative ways and generate new components, with different modes of functionality. Such components, called morphable components, are designed to impose the minimum accepted area and timing overhead, without any reconfiguration overhead. The great advantage of the bottom-up approach is that it can be integrated easily with existing design methodologies and tools, offering great overall performance improvements. The results obtained with different DSP benchmarks in a high-level synthesis environment show an average performance gain of 15%, without any practical datapath area increase, offering uniform and balanced resource utilization.

关键词： Reconfigurable architectures Runtime reconfiguration High level synthesis Design automation Artificial intelligence

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Low power and fast DCT architecture using multiplier-less method

Low power and fast DCT architecture using multiplier-less me...

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2011 Faible Tension Faible Consommation, FTFC 2011

作者： El Aakif, M. Belkouch, S. Chabini, N. Hassani, M.M. Embedded Systems and Digital Control Laboratory National School of Applied Sciences University of Cadi Ayyad Av. Abdelkarim Khattabi Guéliz Marrakech Morocco Department of Electrical and Computer Engineering Royal Military College of Canada Kingston ON Canada Faculty of Sciences Semlalia University of Cadi Ayyad Marrakech Morocco

ISBN: (纸本)9781612846477

In this paper, a low power and fast DCT (Discrete Cosine Transform) using multiplier-less method is presented with a new modified FGA (Flow-Graph Algorithm), which is derived from our previously presented FGA of DCT based on Loeffler algorithm. The multiplier-less method is based on the replacement of multiplications with a minimum number of additions and shifts. The proposed FGA is performed and compared to a previous one. The results of FPGA implementations on Altera Cyclone II show the increase of the maximum frequency, the decrease of the resources usage and the reduction of the dynamic power by 7.2 % at 120 MHz of clock frequency with a new proposed FGA algorithm. Another comparison with recent published results has been done and proves the efficiency of the proposed FGA. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Elucidating the identity of resistance mechanisms to prednisolone exposure in acute lymphoblastic leukemia cells through transcriptomic analysis: A computational approach

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Journal of Clinical Bioinformatics 2011年第1期1卷 1-21页

作者： Sifakis, Emmanouil G. Lambrou, George I. Prentza, Andriana Vlahopoulos, Spiros Koutsouris, Dimitris Tzortzatou-Stathopoulou, Fotini Chatziioannou, Aristotelis A. School of Electrical and Computer Engineering National Technical University of Athens Athens Greece First Department of Pediatrics University of Athens Choremeio Research Laboratory Athens Greece Department of Digital Systems University of Piraeus Piraeus Greece University Research Institute for Genetic and Malignant Diseases of Childhood University of Athens Athens Greece Institute of Biological Research and Biotechnology National Hellenic Research Foundation Athens Greece

Background: It has been shown previously that glucocorticoids exert a dual mechanism of action, entailing cytotoxic, mitogenic as well as cell proliferative and anti-apoptotic responses, in a dose-dependent manner on CCRF-CEM cells at 72 h. Early gene expression response implies a dose-dependent dual mechanism of action of prednisolone too, something reflected on cell state upon 72 h of ***: In this work, a generic, computational microarray data analysis framework is proposed, in order to examine the hypothesis, whether CCRF-CEM cells exhibit an intrinsic or acquired mechanism of resistance and investigate the molecular imprint of this, upon prednisolone treatment. The experimental design enables the examination of both the dose (0 nM, 10 nM, 22 uM, 700 uM) effect of glucocorticoid exposure and the dynamics (early and late, namely 4 h, 72 h) of the molecular response of the cells at the transcriptomic ***: In this work, we demonstrated that CCRF-CEM cells may attain a mixed mechanism of response to glucocorticoids, however, with a clear preference towards an intrinsic mechanism of resistance. Specifically, at 4 h, prednisolone appeared to down-regulate apoptotic genes. Also, low and high prednisolone concentrations up-regulates genes related to metabolism and signal-transduction in both time points, thus favoring cell proliferative actions. In addition, regulation of NF-κB-related genes implies an inherent mechanism of resistance through the established link of NF-κB inflammatory role and GC-induced resistance. The analysis framework applied here highlights prednisolone-activated regulatory mechanisms through identification of early responding sets of genes. On the other hand, study of the prolonged exposure to glucocorticoids (72 h exposure) highlights the effect of homeostatic feedback mechanisms of the treated ***: Overall, it appears that CCRF-CEM cells in this study exhibit a diversified, combined pattern of intrinsic and a

关键词： Acute lymphoblastic leukemia DNA microarray analysis Gene ontology Glucocorticoid resistance Intrinsic vs. acquired

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Design and Implementation of an OFDM System for Vehicular Communications with FPGA Technologies

Design and Implementation of an OFDM System for Vehicular Co...

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International Conference on Design & Technology of Integrated systems in Nanoscale Era

作者： George Kiokes George Economakos Angelos Amditis Nikolaos K. Uzunoglu Institute of Communication and Computer Systems (ICCS) National Technical University of Athens Microprocessors and Digital Systems Laboratory School of Electrical and Computer Engineering National Technical University of Athens Microwaves and Optics Laboratory School of Electrical and Computer Engineering National Technical University of Athens

ISBN: (纸本)9781612848990

This paper presents design and implementation results of an Orthogonal Frequency Division Multiplexing (OFDM) system customized for vehicular ad-hoc networks, based on the IEEE 802.11p standard specifications. The 802.11p is based on the widely spread IEEE 802.11a and intends to support both public safety and licensed private operations over communication channels. OFDM achieves very efficient use of the allocated bandwidth and the main advantage is its robustness to frequency selectivity in wireless environment, like in the case of vehicular communications. The OFDM transceiver implementation presented in this paper is based on FPGA technology and the VHDL hardware description language. The hardware modules designed include QPSK modulator-demodulator, serial to parallel converter, FFT, IFFT. The use of reconfigurable FPGA devices and VHDL descriptions allowed a large number of tests to be carried out for each module, in order to obtain optimum results. The final implementation consists of two identical Xilinx Virtex-4 FPGA development boards (one for the receiver and one for the transmitter), offering among others dual channel high performance ADCs and DACs, required for operation in the licensed ITS band of 5.9 GHz.

关键词： OFDM IEEE 802.11 standards digital Integrated Circuits Reconfigurable Logic Design Automation

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System design and implementation of social interactive robot Nancy

System design and implementation of social interactive robot...

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International Conference on Information Sciences and Interaction Sciences (ICIS)

作者： Shuzhi Sam Ge Chun Fui Liew Yanan Li Institute of Intelligent Systems University of Electronic Science and Technology Chengdu China Social Robotics Laboratory Interactive Digital Media Institute and Department of Electrical and Computer Engineering National University of Singapore Singapore Social Robotics Laboratory Interactive Digital Media Institute and NUS Graduate School for Integrative Sciences and Engineering National University of Singapore Singapore

This paper presents a social interactive robot Nancy that has been developed in Social Robotics laboratory, National University of Singapore. Fundamentally different from factory robots, Nancy's design focuses on social interaction and social intelligent system. The design objectives and consideration are examined in the beginning, followed by the description of hardware and software architectures. Contrast to current existing social robots, Nancy has a graphical user interface (GUI), which acts as an additional channel for human-robot interaction. This GUI helps users to have a better understanding of Nancy's internal states and hence make users feel more comfortable during the interaction with Nancy. Visitors' interaction experience with Nancy is discussed together with Nancy's social skills.

关键词： Robots Graphical user interfaces Servomotors Speech Universal Serial Bus Face Hardware

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Low power and fast DCT architecture using multiplier-less method

Low power and fast DCT architecture using multiplier-less me...

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Faible Tension Faible Consommation (FTFC)

作者： M. El Aakif S. Belkouch N. Chabini M. M. Hassani Embedded Systems and Digital Control Laboratory National School of Applied Sciences University of Cadi Ayyad Marrakech Morocco Department of Electrical and Computer Engineering Royal Military College of Canada Kingston ONT Canada Faculty of Sciences Semlalia University of Cadi Ayyad Marrakech Morocco

关键词： Discrete cosine transforms Hardware computer architecture Power demand Field programmable gate arrays Algorithm design and analysis Equations

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A mixed style architecture for low power multipliers based on a bypass technique

A mixed style architecture for low power multipliers based o...

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5th Conference on Design and Technology of Integrated systems in Nanoscale Era, DTIS 2010

作者： Economakos, George Bekiaris, Dimitris Pekmestzi, Kiamal National Technical University of Athens School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory Heroon Polytechniou 9 GR-15780 Athens Greece

ISBN: (纸本)9781424463404

In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low dynamic power consumption. While this idea offers great savings mainly to array multipliers, due to their regular interconnection scheme, the reduced area and fast speed of tree multipliers is a real temptation for the designer. Therefore, a mixed style architecture, using a traditional, tree based part, combined with a bypass, array based part, is proposed. Through extensive experimentation it has been found that the bypass technique offers minimum power consumption for all cases while the mixed architecture offers a delay*power product improvement ranging from 1.2x to 6.5x, compared to all other architectures. © 2010 IEEE.

关键词： Electric power utilization

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