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International Conference on Design and Technology of Integrated systems in Nanoscale Era (DTIS)

作者： George Economakos Dimitris Bekiaris Kiamal Pekmestzi School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory National and Technical University of Athens Athens Greece

ISBN: (纸本)9781424463381;9781424463404

In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low dynamic power consumption. While this idea offers great savings mainly to array multipliers, due to their regular interconnection scheme, the reduced area and fast speed of tree multipliers is a real temptation for the designer. Therefore, a mixed style architecture, using a traditional, tree based part, combined with a bypass, array based part, is proposed. Through extensive experimentation it has been found that the bypass technique offers minimum power consumption for all cases while the mixed architecture offers a delay*power product improvement ranging from 1.2x to 6.5x, compared to all other architectures.

关键词： Clocks Delay Energy consumption Switching circuits Integrated circuit interconnections Power dissipation Very large scale integration digital signal processing Isolation technology computer architecture

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A mixed style multiplier architecture for low dynamic and leakage power dissipation

A mixed style multiplier architecture for low dynamic and le...

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International Symposium on VLSI Design, Automation and Test

作者： Dimitris Bekiaris George Economakos Kiamal Pekmestzi School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory National and Technical University of Athens Athens Greece

ISBN: (纸本)9781424452699;9781424452712

In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). While this technique offers great dynamic power savings mainly in array multipliers, due to their regular interconnection scheme, it misses the reduced area and fast speed advantages of tree multipliers. Therefore, a mixed style architecture, using a traditional, tree based part, combined with a bypass, array based part, is proposed. Through extensive experimentation it has been found that while the bypass technique offers the minimum dynamic power consumption value, the mixed architecture offers a delay*power product improvement ranging from 1.2x to 6.5x, compared to all other architectures. Furthermore, the tree part of the mixed architecture has enough timing slack to be implemented with high Vth low leakage components, offering an extra 20%-30% leakage power saving, which is a considerable value in deep submicron technologies.

关键词： Power dissipation Clocks Delay Threshold voltage Switching circuits Energy consumption Combinational circuits Timing Capacitance computer architecture

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Construction of dual mode components for reconfiguration aware high-level synthesis 10

Construction of dual mode components for reconfiguration awa...

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Design, Automation and Test in Europe Conference and Exhibition

作者： George Economakos Sotirios Xydis Ioannis Koutras Dimitrios Soudris School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory National and Technical University of Athens Athens Greece

ISBN: (纸本)9783981080162

High-level synthesis has recently started to gain industrial acceptance, due to the improved quality of results and the multi-objective optimizations offered. One optimization area lately addressed is reconfigurable computing, where parts of a DFG are merged and mapped into coarse grained reconfigurable components. This paper presents an alternative approach, the construction of dual mode components which are exchanged with regular components in the resulting RTL architecture. The dual mode components are constructed by exhaustive search for dual mode functional primitives inside the datapath of complicated RTL components. Such components, like multipliers and dividers, that would remain idle in certain control steps, are able to work full-time in two different modes, without any reconfiguration overhead applied to the critical path of the application. The results obtained with different DSP benchmarks show an average performance gain of 15%, without any practical datapath area increase, offering uniform and balanced resource utilization.

关键词： High level synthesis digital signal processing Performance gain Resource management Multiplexing Timing microprocessors digital systems Laboratories computer industry

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High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures

High-Level Synthesis Methodologies for Delay-Area Optimized ...

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IEEE computer Society Annual Symposium on VLSI

作者： Sotirios Xydis Kiamal Pekmestzi Dimitrios Soudris George Economakos Microprocessors and Digital Systems Laboratory Electrical and Computer Engineering Department National and Technical University of Athens Athens Greece

ISBN: (纸本)9781424473212

As Very Large Scale Integration (VLSI) process technology continues to scale down transistor sizes, modern computing devices are becoming extremely complex. In order to face this complexity explosion, the shifting of design methodologies towards higher level of abstraction has been proposed. This high level view of the design procedure enables the automated synthesis of applications' architecture that is written in an application-level description i.e. C/C++. Additionally, it allows designers to explore the tradeoffs between different system and implementation parameters to conclude in an efficient design solution. The work done during this PhD thesis targets the exploration and optimization of the design solutions in a global manner, by focusing on the combined development of novel (i) system-level automated design methodologies/tools and (ii) circuit-level techniques for a specific class of system architectures - reconfigurable systems. Reconfigurable Computing has been proposed as a new paradigm to address the conflicting design requirements for high performance and area efficiency. Towards this direction, fine- and coarse-grained reconfigurable coprocessor architectures have been presented. Unlike fine-grained, coarse-grained architectures (CGA) operate at the word level of granularity exhibiting better power and performance features, close to ASIC solutions. However, a performance-area-power gap still exists for CGAs to overcome ASIC implementations. Thus, new fundamental design problems/questions has been raised. Does this gap be a bridgeable one? How can CGAs shift even closer to ASIC datapaths? In order to address the aforementioned problems, we identified that hardware sharing at the bit-level generates CGAs with performance and area characteristics closer to ASICs than the existing ones. Thus, this thesis proposes new architectural templates and the corresponding high level synthesis methodologies to enable a new shifting on the state-of-the-art of CGAs.

关键词： Optimization Coprocessors Space exploration Hardware Design automation computer architecture Discrete cosine transforms

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Architectural exploration in biomedical hardware design using a novel behavioral synthesis methodology

Architectural exploration in biomedical hardware design usin...

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17th European Signal Processing Conference, EUSIPCO 2009

作者： Economakos, George Microprocessors and Digital Systems Laboratory School of Electrical and Computer Engineering National Technical University of Athens Heroon Polytechniou 9 GR 15780 Zografou Greece

Medical diagnostics are changing rapidly, aided by a new generation of portable equipment and handheld devices that can be carried to the patient's bedside. Processing solutions for such equipment must offer high performance, low power consumption and also, minimize board space and component counts. Such a multi-objective optimization can be performed with behavioral hardware synthesis, offering design quality with significantly reduced design time. In this paper, an architectural exploration of the hardware implementation of a known QRS detection algorithm is performed, following a rapid prototyping approach offered by an advanced behavioral synthesis framework. Experimental results show that with this approach performance improvements are introduced with a fraction of design time, reducing dramatically time-to-market for modern diagnostic devices. © EURASIP, 2009.

关键词： Diagnosis

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Flexible Datapath Synthesis through Arithmetically Optimized Operation Chaining

Flexible Datapath Synthesis through Arithmetically Optimized...

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NASA/ESA Conference on Adaptive Hardware and systems (AHS)

作者： Sotirios Xydis Ioannis Triantafyllou George Economakos Kiamal Pekmestzi School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory National and Technical University of Athens Greece

Datapath synthesis incorporating complex operation templates has been proven extremely efficient especially for the digital signal processing (DSP) application ***, only architectural level optimizations have been reported for the specification and implementation of the operation templates. This paper introduces the consideration of arithmetic level optimizations for template based datapath synthesis. A high performance architecture for the implementation of DSP kernels is presented. It is based on flexible and arithmetically optimized components able to perform a large set of operation templates. A synthesis methodology for optimized mapping of DSP kernels onto the proposed architecture is also presented. Experimental results are reported showing significant gains in execution time, active chip area and power dissipation in comparison to previously published flexible template-based data paths.

关键词： Arithmetic Hardware Kernel digital signal processing Switches Signal synthesis Adders High level synthesis Application specific processors Integrated circuit interconnections

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High-level synthesis with coarse grain reconfigurable components

High-level synthesis with coarse grain reconfigurable compon...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： George Economakos Sotiris Xydis School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory National and Technical University of Athens Athens Greece

High-level synthesis is the process of balancing the distribution of RTL components throughout the execution of applications. However, a lot of balancing and optimization opportunities exist below RTL. In this paper, a coarse grain reconfigurable RTL component that combines a multiplier and a number of additions is presented and involved in high-level synthesis. The gate-level synthesis methodology for this component imposes practically no extra hardware than a normal multiplier while involvement in high-level synthesis is performed with a scheduling postprocessor. Following this approach, components that would remain idle in certain control steps are working full-time in two different modes, without any reconfiguration overhead applied to the critical path of the application. The results obtained with different DSP benchmarks show a maximum performance gain of almost 70% with a 45% datapath area gain.

关键词： High level synthesis Performance gain Adders digital signal processing Hardware design languages Delay Runtime Distributed computing microprocessors digital systems

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Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis

Optimized Reconfigurable RTL Components for Performance Impr...

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Euromicro Symposium on digital System Design

作者： George Economakos Sotiris Xydis School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory National and Technical University of Athens Athens Greece

High-level synthesis is the process of balancing the distribution of RTL components throughout the execution of applications. However, a lot of balancing and optimization opportunities exist below RTL. In this paper, a coarse grain reconfigurable RTL component that combines a multiplier and a number of additions is presented and involved in high-level synthesis. The gate-level synthesis methodology proposed for this component imposes practically no extra hardware than a normal multiplier, as shown after extensive experimentation. Involvement in high-level synthesis is performed with a scheduling postprocessor. Following this approach, components that would remain idle in certain control steps are working full-time in two different modes, without any reconfiguration overhead applied to the critical path of the application. The results obtained with different DSP benchmarks show an average performance gain of 15% without practically any datapath area increase.

关键词： High level synthesis Routing Software maintenance Field programmable gate arrays digital systems computer architecture Design optimization High performance computing Hardware design languages Software performance

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A system-level design methodology for application-specific networks-on-chip

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Journal of Embedded Computing 2009年第3期3卷 167-177页

作者： Bartzas, Alexandros Papadopoulos, Lazaros Soudris, Dimitrios VLSI Design and Testing Center Department of Electrical and Computer Engineering Democritus University of Thrace 67100 Xanthi Greece Microprocessors and Digital Systems Lab School of Electrical and Computer Engineering National Technical University of Athens 15780 Zografou Greece

Modern embedded consumer devices execute complex network and multimedia applications that require high performance and low energy consumption. For implementing complex applications on Network-on-Chips (NoCs), a design methodology is needed for performing exploration at NoC system-level, in order to select the optimal application-specific NoC architecture, serving the application requirements in the best way. The design methodology we present in this paper is based on the exploration of different NoC characteristics and is supported by a flexible NoC simulator which provides the essential evaluation metrics in order to select the optimal communication parameters of the NoC architectures. We illustrated that it is possible with the evaluation metrics provided by the simulator we present, to perform exploration of several NoC aspects and select the optimal communication characteristics for NoC platforms having network and multimedia applications as the target domains. With our methodology we can achieve a gain of 57% in the Energy x Delay Product on average.

关键词： Network-on-chip topology exploration application-specific

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ARCHITECTURAL EXPLORATION IN BIOMEDICAL HARDWARE DESIGN USING A NOVEL BEHAVIORAL SYNTHESIS METHODOLOGY

ARCHITECTURAL EXPLORATION IN BIOMEDICAL HARDWARE DESIGN USIN...

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European signal processing conference

作者： George Economakos Microprocessors and Digital Systems Laboratory School of Electrical and Computer EngineeringNational Technical University of Athens Heroon Polytechniou 9 GR 15780 Zografou Greece

ISBN: (纸本)9781617388767

关键词： design year computer hardware computer hardware design Exploration Portable equipment Detection algorithms synthesis

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