检索结果-内蒙古大学图书馆

FPGA-based reflection image removal using cognitive neural networks

Applied Nanoscience (Switzerland) 2023年第3期13卷 2539-2553页

作者： Saptalakar, Bairu K. Latte, Mrityunjaya V Department of Electronics and Communication Engineering SDM College of Engineering and Technology Karnataka Dharwad580002 India Department of Electronics and Communication Engineering JSS Academy of Technical Education Karnataka Bengaluru560060 India

There is an enormous increase in the resource usage and certain process is required to satisfy the user requirement. Thus, there is a process integration on IoT and data analytics which paves the way for the smart city development. The energy management plays a crucial role based on the processing of image dataset and optimization using the artificial intelligence. To increase the visibility of the image based on the reflection concept, cognitive models are used by relocating the clear glass images. The above process is used widely in computer vision applications as it is ill nature and makes the additional precursors more challenging. Then, eliminating reflections problem is considered for various heuristic observations or other assumptions and it fulfills in practical conditions. In this paper, we generalize the assumptions for issues of reflection based on usage of different information or impose new limitations elimination. The image elimination helps in effective energy utilization by managing the resource through CNN, i.e., optimization techniques of cognitive networks. To overcome the various optimization functions, long computational time required and reflection removal methods, i.e., conventional have not guaranteed their performance. It helps in developing the smart cities as energy plays a significant role as the propose system is integrated with IoT and data analytics. As FPGA system is deployed, it can screen the images by providing effectively the sustainable policies with energy efficient platform through data compression. In the performance analysis, the proposed algorithm is effective as compared with current approaches using CNN methods. Parallel processing of Images in Digital Signal Processing tools will create degradation of the images and it is difficult to achieve high performance, so the implementation is done using FPGA. © 2022, King Abdulaziz City for Science and technology.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Recognition for underground voids in C-scans based on GMM-HMM

引用

Journal of Systems engineering and electronics 2025年第1期36卷 82-94页

作者： BAI Xu LI Yuhao GUO Shizeng LIU Jinlong WEN Zhitao LI Hongrui ZHANG Jiayan School of Electronics and Information Engineering Harbin Institute of TechnologyHarbin 150001China

Ground penetrating radar(GPR),as a fast,efficient,and non-destructive detection device,holds great potential for the detection of shallow subsurface environments,such as urban road subsurface ***,the interpretation of GPR echo images often relies on manual recognition by experienced *** order to address the automatic interpretation of cavity targets in GPR echo images,a recognition-algorithm based on Gaussian mixed model-hidden Markov model(GMM-HMM)is proposed,which can recognize three dimensional(3D)underground voids ***,energy detection on the echo images is performed,whereby the data is preprocessed and ***,edge histogram descriptor(EHD),histogram of oriented gradient(HOG),and Log-Gabor filters are used to extract features from the *** traditional method can only be applied to 2D images and pre-processing is required for C-scan ***,the aggregated features are fed into the GMM-HMM for classification and compared with two other methods,long short-term memory(LSTM)and gate recurrent unit(GRU).By testing on a simulated dataset,an accuracy rate of 90%is obtained,demonstrating the effectiveness and efficiency of our proposed method.

关键词： ground penetrating rader(GPR) recognition edge histogram descriptor(EHD) histogram of oriented gradient(HOG) Log-Gabor filter

来源：评论

学校读者我要写书评

暂无评论

Design and Implementation of Knee Angle Recovery Companion Kit: A Knee Flex Rehab Aid System 9

Design and Implementation of Knee Angle Recovery Companion K...

引用

9th International Conference on Science, technology, engineering and Mathematics, ICONSTEM 2024

作者： Ram Nivas, D. Krishnaraj, R. Kathirvelu, M. Ishwarya Niranjana, M. Kpr Institute of Engineering And Technology Department of Electronics And Communication Engineering Coimbatore India Bannari Amman Institute of Technology Department of Electronics And Communication Engineering Erode India

ISBN: (数字)9798350365092

ISBN: (纸本)9798350365092

This paper aims to design a biotelemetry system for helping the knee patients. Patients with haemophilia typically require total knee replacement surgery, which significantly enhances their quality of life. But, haemophiliacs are more at risk for bleeding and infection from this operation than osteoarthritis patients are. Implanting prosthetic parts with cement that has antibiotics in it is advised. For two weeks, it is crucial to keep the replacement clotting factor at a level of 100%. The majority of knee replacements can't bend as far as your native knee can. This project is used to tackle these issues and provide better recovery using ESP 32 microcontroller, mems sensor, DHT sensor and wetness detection sensor. The sensor values will be continuously monitored and updated to the physiotherapist through a mobile application using Blynk server. A comforting device is kept around the knee for the purpose of massaging. This technology promises to enhance the safety and effectiveness of knee implants and improve the quality of life for patients with knee replacement. © 2024 IEEE.

关键词： Implants (surgical)

来源：评论

学校读者我要写书评

暂无评论

Kalman filter-based deep fused architecture for knee angle estimation

引用

Multimedia Tools and Applications 2025年第15期84卷 15173-15203页

作者： Satheesh Kumar, E. Sundar, S. School of Electronics Engineering Vellore Institute of Technology Tamil Nadu Vellore India

Accurate measurements of joint angle are crucial for gait assessment applications. IMUs, which have a wide range of applications, can be a valuable resource for learning about the kinematics of gait. However, the assessment accuracy of the gait kinematics as well as consequently joint angles is only moderate due to the nonlinear process of human locomotion. In this research, a new joint measurement system with two key components estimation of knee angle and estimation of roll, pitch, and yaw is proposed. A training dataset and a testing dataset are separated within the dataset. The training and test datasets are filtered using the extended Kalman Filter. In this instance, roll, pitch, and yaw data are taken into consideration as input for the knee angle estimation in order to predict the appropriate filtered roll, pitch, and yaw as well. The Improved Deep Convolutional Neural Networks (IDCNN) and Bidirectional Long Short-Term Memory (Bi-LSTM) models are combined to form a Hybrid Classification Model (HCM) framework, which is used in the second stage to estimate the knee angle. Additionally, the suggested HCM’s efficacy is contrasted with that of other conventional classifiers using various metrics. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.

关键词： Kalman filters

来源：评论

学校读者我要写书评

暂无评论

MOS Transistor-Based Memristor Emulator for Realization of Universal Logic Gates

MOS Transistor-Based Memristor Emulator for Realization of U...

引用

2024 IEEE Silchar Subsection Annual Conference, SILCON 2024

作者： Choudhury, Debalina Roy Dhakar, Ashish Chaurasiya, Rajneesh Gupta, Goutam Kumar Nit Agartala Department of Electronics & Communication Engineering Agartala India Amrita School of Engineering Department of Electronics & Communication Engineering Chennai India

ISBN: (纸本)9798331540821

Memristors are now widely used in new computing systems as device-level components. This research shows a circuit that effectively emulates memristor behavior by utilizing the Metal oxide semiconductor field effect transistor's dynamic threshold feature. The circuit is meant to be simple and easy to integrate into existing MOSFET technology, removing the need for additional DC bias and simplifying implementation in various electronic applications. A novel ground memristor emulator with three MOSFETs and an external capacitor has been demonstrated and compared with another grounded memristor model with only two MOSFETs. Two transistor memristor emulator model shows simple circuit, low power consumption, and high-frequency operation, making it suitable for a wide range of applications, such as logic gates. Simulations with the Cadence Virtuoso-Spectre tool's 90 nm CMOS GPDK parameter theoretically justified the parameters regarding memristor emulator circuits. © 2024 IEEE.

关键词： CMOS integrated circuits

来源：评论

学校读者我要写书评

暂无评论

Performance Analysis of Fast & Power Efficient Dynamic Comparator Topologies 2

Performance Analysis of Fast & Power Efficient Dynamic Compa...

引用

2nd IEEE International Conference on Device Intelligence, Computing and communication Technologies, DICCT 2024

作者： Anand, Agyenya Yadav, Anurag Wairva, Subodh Institute of Engineering and Technology Department of Electronics and Communication Engineering Lucknow India

ISBN: (纸本)9798350372847

Comparator is an important block of ADCs. Dynamic comparators have replaced static comparators as these are fast and also address the issue of huge static power dissipation in static comparators. Therefore, ADCs, which require high speed and less power consumption, use dynamic regenerative comparators. These comparators are clock based and has two stages: a latch stage and a preamplifier stage. Fast operation, less power consumption, high accuracy, and less offset are some desirable features of a comparator. Any one topology of comparator cannot provide all these features. Thus, an effort has been made in this work to analyze performance of some topologies of dynamic comparators based on parameters like power, delay, slew rate and number of transistors. So, it is easy to select suitable comparator topology based on required application. This paper comprises of comparison between three topologies of dynamic comparators which are as follows: Shared charge reset technique based dynamic latched comparator (SCRDLC), Low-Power 1Volt supply Dynamic Comparator (LP1VSDC) and Cascode Cross-Coupled Stage High-Speed Dynamic Comparator (CCSHSDC). These comparators are simulated on Cadence Virtuoso simulation software using 45-nm technology. © 2024 IEEE.

关键词： Comparators (optical)

来源：评论

学校读者我要写书评

暂无评论

An On-chip Fractal Antenna using Defective Ground Structure for Compact RFIC Applications

An On-chip Fractal Antenna using Defective Ground Structure ...

引用

2024 IEEE Microwaves, Antennas, and Propagation Conference, MAPCON 2024

作者： Singh, Harshavardhan Mandal, Sujit Kumar Department of Electronics & Communication Engineering Amrita School of Engineering Amrita Vishwa Vidyapeetham Coimbatore India Department of Electronics & Communication Engineering National Institute of Technology Durgapur Durgapur713209 India

ISBN: (纸本)9798350379693

Radio frequency integrated circuits (RFIC) are the vital component of electronic devices utilizing system-on-chip (SoC) architecture for communication. To make these devices truly wireless and miniaturized, an on-chip antenna (OCA) plays a significant role. This paper presents the design of a miniaturized OCA for Ku-band applications. In general, at lower microwave frequencies, to achieve efficient radiation characteristics from compact OCA is quite challenging. Here, the combination of DGS along with fractal design methods is employed to boost the antenna's bandwidth (BW) to 7.22 GHz across the entire 12 to 18 GHz (Ku-Band) range at center frequency of 15 GHz. The OCA is integrated within a compact area of π22 mm2 and reflects a gain and efficiency of -19.76 dBi and 55.6%, respectively. Moreover, the outcomes of simulation and characterization of fabricated design display very good alignment together. © 2024 IEEE.

关键词： System-on-chip

来源：评论

学校读者我要写书评

暂无评论

Design of High-Speed Hybrid Vedic Multiplier for DSP Application

Design of High-Speed Hybrid Vedic Multiplier for DSP Applica...

引用

2024 International Conference on Distributed Systems, Computer Networks and Cybersecurity, ICDSCNC 2024

作者： Shankar, Smitha Sharath Rohith, S. Rohan, Nadiminti Rakesh Eswar, Kannali P C Bharghav, V.R. Nitte Meenakshi Institute of Technology Department of Electronics and Communication Engineering Bengaluru India Nagarjuna College of Engineering and Technology Department of Electronics and Communication Engineering Bengaluru India

ISBN: (纸本)9798350375442

The main component in the Digital Signal Processing (DSP) system is Multiply and Accumulate (MAC) unit and a multiplier is an essential part in the MAC unit. The MAC unit's performance in DSP applications is heavily influenced by the characteristics of the multiplier, including its speed, area efficiency and power consumption. Optimizing these parameters is essential for achieving efficient and high-performance signal processing applications. The proposed work shows the design of a 16-bit MAC unit based on an 8-bit hybrid Vedic multiplier. The design of an 8-bit hybrid Vedic multiplier uses Kagge stone adder and a carry skip adder. The complete design is implemented in Verilog *** Xilinx Vivado, synthesis and simulations were carried out. The proposed MAC unit with Hybrid Vedic multiplier provides a notable improvement in power, area, and latency compared to conventional MAC unit. Finally, it is observed that the delay time for an 8×8-bit Hybrid Vedic multiplier was 11.941ns, while it was 8.053ns for a 16-bit MAC unit Area, delay and power are significantly improved by the proposed design. © 2024 IEEE.

关键词： carry skip adder kagge stone adder multiply and accumulate (MAC) unit urdhva tiryagbhyam urdhva tiryakbhyam (UD) vedic mutiplier (VM)

来源：评论

学校读者我要写书评

暂无评论

Outage Probability Analysis of Dual Hop FSO Convergent with RF-UWOC Hybrid Link for SAGSIN in 6G-IoT Systems

Outage Probability Analysis of Dual Hop FSO Convergent with ...

引用

2024 International Conference on Smart electronics and communication Systems, ISENSE 2024

作者： Rajeshwari, V. Ishana Chellam, S. Yukta Sri, C.K. Kamatchi, Kavitha Suveetha Dhanaselvam, P. Karthikeyan, B. Krishnan, Prabu Velammal College of Engineering and Technology Department of Electronics and Communication Engineering Madurai India National Institute of Technology Karnataka Department of Electronics and Communication Engineering Surathkal India

ISBN: (纸本)9798331528126

This paper analyses the effectiveness of a novel hybrid communication system designed for a space-air-ground-sea integrated network (SAGSIN) within 6G Internet of Things (6G-IoT) environments. The system employs a dual-hop mechanism, featuring a free-space optical (FSO) link with a Malaga distribution for communication between ground and ships, along with a hybrid Radio Frequency - Underwater Wireless Optical communication (RF-UWOC) link characterized by Nakagami-m and exponential generalized Gamma distributions for ship-to-underwater Autonomous Vehicle (AUV) communication. In this configuration, the ship serves as a Decode-and-Forward relay, where the RF link bolsters system reliability, and the UWOC link ensures secure communication. To optimize overall performance, the system implements a selection combining technique to identify the best signal from both RF and UWOC links. The paper evaluates the end-to-end cumulative distribution function (CDF) of the channel through the Meijer-G hypergeometric function. It also examines the outage probability of the proposed system across various weather conditions in the FSO channel, the effects of the Nakagami fading parameter m, and variations in salinity in the UWOC link. © 2024 IEEE.

关键词： Distribution functions

来源：评论

学校读者我要写书评

暂无评论

Analysis Of Traffic Sign Recognition Using Artificial Neural Network Algorithm Compared With Accuracy Of Recurrent Neural Networks 9

Analysis Of Traffic Sign Recognition Using Artificial Neural...

引用

9th International Conference on Applying New technology in Green Buildings, ATiGB 2024

作者： Amos, P. Narendran, S. Keerthivasan, M. Institute of Electronics and Communication Engineering Saveetha School of Engineering Simats Department of Nanotechnology Chennai India Institute of Electronics and Communication Engineering Saveetha School of Engineering Simats Chennai India

ISBN: (纸本)9798331505042

The purpose of this work is to improve Traffic sign recognition using machine learning to improve comprehension of traffic signs. The Novel Artificial Neural Network (ANN) method is compared with Recurrent Neural Network (RNN) to find accuracy. Symbols on the traffic sign boards are used as an image processing input picture. Novel Artificial Neural Network (ANN) (Group 1) has ten samples and Recurrent Neural Network (RNN) (Group 2) has ten samples and in total 146 samples. With the help of image analysis, a Novel Artificial Neural Network (ANN) and Recurrent Neural Network (RNN) are used to predict the accuracy of traffic sign recognition. The training and testing splits are varied for each network type. The G Power test used is about 85% with *** the process is done for αa=0.05 and N=0.85 iterations. Novel Artificial Neural Network (ANN) (90.585 %) has the increased accuracy over Recurrent Neural Network (RNN) (76.649%) with a statistical significance value of 0.042 (p © 2024 IEEE.

关键词： Recurrent neural networks

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：