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17th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2024

作者： Zhao, Mengyao Zheng, Yifei Ma, Yanfeng Sun, Yuan Wang, Denggui Pan, Chuanqi Zhou, Jianjun Li, Sheng Zhang, Long Liu, Siyang Sun, Weifeng National ASIC System Engineering Research Center School of Integrated Circuits Southeast University Jiangsu Nanjing China National Key Laboratory of Solid-State Microwave Devices and Circuits Jiangsu Nanjing China

ISBN: (纸本)9798350361834

We fabricate a 200V monolithic GaN half-bridge power IC featuring an integrated substrate termination network (ISTN). The ISTN utilizes two-dimensional electron gas resistors to dynamically control the substrate potential so that detrimental back-gating effects and dynamic on-resistance ( R o n ) degradation is effectively suppressed. The proposed GaN power IC scheme with ISTN demonstrates remarkable performance by minimizing the increase in dynamic R o n for both the high-side and low-side HEMT at power supply of 200V, respectively. The fabricated monolithic ISTN can minimize parasitic elements compared with the board-level substrate termination network in previous work, while no additional process complexity is required. © 2024 IEEE.

关键词： Gallium nitride

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An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process 14

An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time a...

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14th IEEE International Conference on asic, asicON 2021

作者： Hu, Xianwu Li, Dongyang Wang, Yu Feng, Jiayun Ma, Zizhao Wang, Shaohao Min, Tai Zeng, Xiaoyang Xie, Yufeng Fudan University State Key Laboratory of ASIC and System School of Microelectronics Shanghai200433 China

ISBN: (纸本)9781665411493

Accessing data and programs from off-chip memories cost lots of time and energy. In order to reduce this consumption, an 8Kb 2T2MTJ STT-MRAM design is proposed to serve as an alternative on-chip memory to store OS programs. An optimized SA suitable for low input-voltage, combined with the 2T2MTJ cell structure we used, could achieve high read speed as well as low energy consumption. A time-adjustable write signal generator help to choose the optimized point of write time and energy consumption in different application scenarios. This design adopts 40-nm technology and achieves 2.6ns read access time with 240 F2 cell area. © 2021 IEEE.

关键词： Energy utilization

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A Comprehensive and Efficient Instruction-level Testing Method for Processor

A Comprehensive and Efficient Instruction-level Testing Meth...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Zixin Yang Zhichao Wei Huanlin Luo Jian Wang Jinmei Lai State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China Shanghai Academy of Spaceflight Technology Shanghai China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

Testing of the processor is crucial, which necessitates a comprehensive test set to ensure an efficient and thorough coverage. We herein propose an Equivalence Class Partitioning and Boundary Value Analysis (ECP-BVA) constrained instruction stream generation method on coverage-guided fuzzing (CGF). The updated ECP-BVA constraints mutate the instruction field to maximize the coverage metrics. The accelerated coverage-guided fuzzing skipes redundant instructions to improve the testing efficiency. An efficient test set is built by fuzzing and the experimential results indicate that our method can maximize coverage metrics close to 100% in a short time, thereby ensuring a comprehensive and efficient coverage for processor testing.

关键词： Measurement Integrated circuit technology Life estimation Fuzzing Testing

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Algorithm/Hardware Co-Design Configurable SAR ADC with Low Power for Computing-in-Memory in 28nm CMOS 14

Algorithm/Hardware Co-Design Configurable SAR ADC with Low P...

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14th IEEE International Conference on asic, asicON 2021

作者： Guo, Zhiwang Chen, Deyang Xue, Xiaoyong Fudan University State Key Laboratory of ASIC and System School of Microelectronics Shanghai201203 China

ISBN: (纸本)9781665411493

With the development of computing-in-memory (CIM) in machine learning (ML) technology, we need higher precision to improve the performance of neural networks (NN). However, analog-to-digital converter (ADC) area and power consumption occupy a large part of the whole chip. This work presents an energy-efficient successive-approximation-register (SAR) ADC to diminish the power problem in CIM without destroying the initial NN structure. Firstly, we propose a configurable SAR ADC with various operating thresholds to deal with different precision of weight including 4-bit weight and high precision weight. Secondly, a circuit-algorithm co-design scheme program the operating mode and cycle of the bit line in ADC to improve energy utilization. The prototype in 28 nm CMOS technology occupies 871.22 um2. It consumes 37.88uW from a 0.9V supply at 50MHz. The energy efficiency of ADC in CIM can be increased at most 20.72% 40.44%. © 2021 IEEE.

关键词： Analog to digital conversion

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RG_VIPS: A Simple Cache Coherence Protocol Based on Region-Grain Directories 16

RG_VIPS: A Simple Cache Coherence Protocol Based on Region-G...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Liu, Yan-Wei Qiu, Yu-Di Tang, Yu-Xin Jiao, Jie Zhang, Peng Fan, Yi-Bo Fudan University State Key Laboratory of Asic and System Department of Microelectronics Shanghai China Peking University Advanced Institute of Information Technology China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

As the number of cores in large-scale chip multiprocessors (CMPs) grows, the complexity and overhead of directory-based cache coherence protocols become increasingly important. To reduce the cost of coherence protocol, previous studies classified data into private and shared, and used different coherence protocols for them. On the one hand, private data can be taken out of coherence. On the other hand, because of the spatial locality of private data, a coarse-grained directory can be used to reduce the directory storage. This paper proposes RG_VIPS, a simple coherence protocol based on region granularity directory. We use a write-through protocol for private data and a write-back protocol for shared data. Compared to previous work VIPS, RG_VIPS eliminates OS dependencies and also implements a simple cache coherence protocol (only two stable protocol states, Valid and Invalid) with finer granularity. Simulation of a 16-core CMP with PARSEC shows that the RG_VIPS protocol has little impact on the performance while simplifying the protocol. © 2022 IEEE.

关键词： Cache memory

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Highly sensitive and stable β-Ga_(2)O_(3) DUV phototransistor with local back-gate structure and its neuromorphic application

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Nano Research 2022年第10期15卷 9359-9367页

作者： Xiao-Xi Li Guang Zeng Yu-Chun Li Qiu-Jun Yu Meng-Yang Liu Li-Yuan Zhu Wenjun Liu Ying-Guo Yang David Wei Zhang Hong-Liang Lu State Key Laboratory of ASIC and System Shanghai Institute of Intelligent Electronics&SystemsSchool of MicroelectronicsFudan UniversityShanghai 200433China Shanghai Synchrotron Radiation Facility(SSRF) Zhangjiang LabShanghai Advanced Research Institute&Shanghai Institute of Applied PhysicsChinese Academy of SciencesShanghai 201204China

Deep ultraviolet(DUV)phototransistors are key integral of optoelectronics bearing a wide spectrum of applications in flame sensor,military detector,oil spill detection,biological sensor,and artificial intelligence *** order to further improve the responsivity of UV photodetectors based onβ-Ga_(2)O_(3),in present work,high-performanceβ-Ga_(2)O_(3) phototransistors with local back-gate structure were experimentally *** phototransistor shows excellent DUV photoelectrical performance with a high responsivity of 1.01×107 A/W,a high external quantum efficiency of 5.02×109%,a sensitive detectivity of 2.98×1015 Jones,and a fast rise time of 0.2 s under 250 nm ***,first-principles calculations reveal the decent stability ofβGa_(2)O_(3) nanosheet against oxidation and humidity without significant performance ***,the hexagonal boron nitride(h-BN)/β-Ga_(2)O_(3) phototransistor can behave as a photonic synapse with ultralow power consumption of~9.6 fJ per spike,which shows its potential for neuromorphic computing tasks such as facial ***β-Ga_(2)O_(3) phototransistor will provide a perspective for the next generation optoelectrical systems.

关键词： β-Ga_(2)O_(3)phototransistors local back-gate responsivity stability photonic synapse

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稀疏二维突触和CMOS神经元混合神经形态硬件用于字符识别

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Science Bulletin 2023年第20期68卷 2336-2343,M0005页

作者：薛思惟王水源吴天祥邸紫烨许诺孙一博曾超凡马顺利周鹏 Shanghai Key Laboratory for Future Computing Hardware and System School of MicroelectronicsFudan UniversityShanghai 200433China State Key Laboratory of ASIC and System School of Information Science and TechnologyFudan UniversityShanghai 200433China Frontier Institute of Chip and System&Qizhi Institute Fudan UniversityShanghai 200433China Hubei Yangtze Memory Laboratories Wuhan 430205China

神经形态计算能够有效处理数密集型任务.本文提出一种基于二维MoS2突触和CMOS神经元混合集成的神经形态硬件系统,可兼具二维突触器件的灵活可塑性与CMOS神经元的成熟度、可靠性.受益于混合集成,进一步提出特征提取和频率编码方式,降低... 详细信息

神经形态计算能够有效处理数密集型任务.本文提出一种基于二维MoS2突触和CMOS神经元混合集成的神经形态硬件系统,可兼具二维突触器件的灵活可塑性与CMOS神经元的成熟度、可靠性.受益于混合集成,进一步提出特征提取和频率编码方式,降低了硬件所需的突触与神经元数量;基于板级全硬件实现高准确率(98.8%)和低功耗(11.4μW)的字符识别功能.本工作为构建高面积效率和能量效率的神经形态硬件系统提供了一个可行的方案.

关键词：字符识别频率编码特征提取硬件系统神经元能量效率混合集成突触

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Integrated Device for Controllable Droplet Generation and Detection on Open Array Chip 16th

Integrated Device for Controllable Droplet Generation and De...

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16th International Conference on Intelligent Robotics and Applications, ICIRA 2023

作者： Zhou, Zijian Wang, Jie Li, Yuxin Zhou, Jia Du, Lin School of Mechanical Engineering University of Shanghai for Science and Technology Shanghai200433 China School of Optical-Electrical and Computer Engineering University of Shanghai for Science and Technology Shanghai200433 China State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai200433 China

ISBN: (纸本)9789819965007

The open array chip is an incredibly valuable tool for analyzing single molecule levels. Its efficiency, speed, compatibility, and precision make it an essential part of this process. However, efficient sample addition has become a significant challenge in the development of open array chips due to the coupling of the solid-liquid interface and the need for high-precision control. To address this challenge, we have developed an integrated adding sample device using technology of generates and detects controllable droplets array based on an open array chip with a biomimetic structure. This device combines a microfluidic chip, image detection, and smear speed regulation. We have studied the factors that affect the efficiency of sample loading, such as the number, speed and fluctuation of smears, and microwell size. The experiments have shown that the open array chip with the microwell’s diameter of 350 µm can generate arrays of ~470/cm2 ~8 nL droplets, significantly reducing controlled speed fluctuation errors by7.24% and volume fluctuation errors by 24% compared to traditional manual ways. The device has also displayed excellent performance on chips with microwell diameters of 120, 350, 700, and 1300 µm, respectively, with a notable first-time success rate of up to 91% on chips with microwell diameters of 120 µm. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023.

关键词： Microfluidic chips

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Sharp-Switching Devices with Positive Feedback Mechanisms Based on Silicon-On-Insulator Substrate 16

Sharp-Switching Devices with Positive Feedback Mechanisms Ba...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Chen, Yingxin Wang, Haihua Wan, Jing Fudan University State Key Laboratory of Asic and System School of Information Science and Technology Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

In this work, we demonstrate Z2-FET (zero subthreshold swing and zero impact ionization FET) and UJ-FET (unijunction FET) on silicon-on-insulator substrate utilizing a CMOS-compatible process. Attributed to novel positive feedback mechanisms, the devices can break the subthreshold swing (SS) limitation in conventional MOSFET and exhibit sharp-switching characteristics. Based on the positive feedback between carrier flow and band modulation, the fabricated Z2-FET has been demonstrated with SS of 14.2 mV/dec and ION/IOFF ratio of 1.5×107. Based on the positive feedback between junction voltage and carrier injection, the fabricated UJ-FET has been demonstrated with SS of 1.5 mV/dec and ION/IOFF ratio of 3.4×107. © 2022 IEEE.

关键词： Impact ionization

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Comprehensive Analysis of Duty-Cycle Induced Degradations in HfxZr1-xO2-Based Ferroelectric Capacitors: Behavior, Modeling, and Optimization

Comprehensive Analysis of Duty-Cycle Induced Degradations in...

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2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024

作者： Feng, Guan Li, Yu Jiang, Hao Wang, Xiaodong Sun, Yize Wei, Yingfen Liu, Qi Liu, Ming Frontier Institute of Chip and System Fudan University State Key Laboratory of Integrated Chips and Systems Shanghai200433 China School of Microelectronics Fudan University Shanghai200433 China

ISBN: (纸本)9798350361469

This work systematically studies degradations in HfxZr1-xO2 (HZO)-based ferroelectric (FE) capacitors (FeCaps) under pulses with different duty cycles (DCs): 1) a larger drop in the switchable polarization (Psw) and shift in the coercive voltage (Vc) by duty-cycling are observed when compared with conventional endurance and retention tests;2) through physical modeling, the wider spread of the generated oxygen vacancies (Vos) during duty-cycling leads to stronger domain pinning and the formation of a larger built-in field (Ebi), which explains the above observation;3) optimizations through engineering the stack and composition of the HZO FE layer are proposed and validated on 128Kbit 2T2C FeRAM chips. © 2024 IEEE.

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