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International Conference on asic

作者： Yishan Zhang Zhiyong Zhang Chang Wu School of Microelectronics State-Key Lab of ASIC and System Fudan University Shanghai China Shanghai Fudan Microelectronics Group Co. Ltd Shanghai China

As design goes into multi-billion transistors, the synthesis runtime becomes an important issue, particularly for design verification and prototyping, as one may run the synthesis many times with design change. Module-by-module synthesis with multi-threading is a natural solution for fast synthesis, however, at the cost of quality of results (QoR) degradation. Besides, multi-thread speedup may not be so good due to very uneven sizes of the modules. In this paper, we propose a design hierarchy restructuring based multi-thread synthesis algorithm for large-scale designs. Small module flattening and large module partitioning are used to create moderate size design modules. Our experimental results show that our algorithm can produce results within 3% area increase and 21.3x speedup over the flat synthesis flow.

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Low-Resistance Cu–Cu Bonding With the Formic Acid-Treated Co Passivation Layer

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IEEE Transactions on Electron Devices 2025年

作者： Shao, Yun-Hao Chen, Gui Wu, Xinwei Xie, Haijiao Qu, Xin-Ping Fudan University State Key Laboratory of ASIC and System School of Microelectronics Shanghai 200433 China Hangzhou Yanqu Information Technology Company Ltd Xihu Zhejiang Hangzhou 310003 China

The Cu–Cu bonding with formic acid-treated Co passivation layer was successfully achieved at 230 °C under atmospheric pressure, resulting in high bonding strength. TEM and energy-dispersive X-ray spectroscopy (EDS) characterization of the bonding interface has revealed that the reduction of oxides through formic acid treatment (FAT) promoted the merging of Co grains while concurrently minimizing the concentration of Cu in center area. The sample with FAT achieved ultralow contact resistance of 3.58 × 10^-8 Ω⋅cm² at 250°C, lower than that without FAT. We analyzed the reasons for the decrease in contact resistance from the bonding interface and found that FAT reduced the surface roughness and oxides, resulting in better bonding of the Co passivation layer and reduced electron scattering. It was concluded that an ideal bonding interface necessitated minimal electron scattering. © 1963-2012 IEEE.

关键词： 3-D integration Co passivation layer contact resistance Cu–Cu bonding formic acid treatment (FAT)

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Double Side Interfacial Optimization for Low-Temperature Stable CsPbI_(2)Br Perovskite Solar Cells with High Efficiency Beyond 16%

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Energy & Environmental Materials 2022年第2期5卷 637-644页

作者： Jing Ma Jie Su Zhenhua Lin Jian He Long Zhou Tao Li Jincheng Zhang Shengzhong Liu Jingjing Chang Yue Hao State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology Shaanxi Joint Key Laboratory of GrapheneSchool of MicroelectronicsXidian UniversityXi’an 710071China Advanced Interdisciplinary Research Center for Flexible Electronics Xidian UniversityXi’an 710071China Centre for Spintronics and Quantum System State Key Laboratory for Mechanical Behavior of MaterialsSchool of Materials Science and EngineeringXi’an Jiaotong UniversityXi’an 710049China Key Laboratory of Applied Surface and Colloid Chemistry National Ministry of Education Shaanxi Engineering Lab for Advanced Energy TechnologySchool of Materials Science and EngineeringShaanxi Normal UniversityXi’an 710119China

CsPbI_(2)Br perovskite solar cells have achieved rapid development owing to their exceptional optoelectronic properties and relatively outstanding ***,open-circuit voltage(Voc)loss caused by band mismatch and charge recombination between perovskite and charge transporting layer is one of the crucial obstacles to further improve the device ***,we proposed a bilayer electron transport layer ZnO(bottom)/SnO_(2)(top)to reduce the Voc loss(Eloss)and promote device Voc by ZnO insert layer thickness modulation,which could improve the efficiency of charge carrier extraction/transfer and suppress the charge carrier *** addition,guanidinium iodide top surface treatment is used to further reduce the trap density,stabilize the perovskite film and align the energy levels,which promotes the fill factor,short-circuit current density(Jsc),and stability of the *** a result,the champion cell of double-side optimized CsPbI_(2)Br perovskite solar cells exhibits an extraordinary efficiency of 16.25%with the best Voc as high as 1.27 V and excellent thermal and storage stability.

关键词： CsPbI_(2)Br dual interfacial optimization high performance low temperature perovskite solar cells

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Journal of Semiconductors 2021年第2期42卷 106-107页

作者： Zhaowu Tang Chunsen Liu Senfeng Zeng Xiaohe Huang Liwei Liu Jiayi Li Yugang Jiang David Wei Zhang Peng Zhou State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China School of Computer Science Fudan UniversityShanghai 200433China

The recently reported quasi-nonvolatile memory based on semi-floating gate architecture has attracted extensive attention thanks to its potential to bridge the large gap between volatile and nonvolatile ***,the further extension of the refresh time in quasi-nonvolatile memory is limited by the charge leakage through the p-n ***,based on the density of states engineered van der Waals heterostructures,the leakage of electrons from the floating gate to the channel is greatly *** a result,the refresh time is effectively extended to more than 100 s,which is the longest among all previously reported quasi-nonvolatile *** work provides a new idea to enhance the refresh time of quasi-nonvolatile memory by the density of states engineering and demonstrates great application potential for high-speed and low-power memory technology.

关键词： quasi-nonvolatile memory refresh time density of states engineering

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A Reusable AI acceleration Architecture based on Matrix Multiplication for Convolutional Neural Network with Digital Signal ProcessingTasks

A Reusable AI acceleration Architecture based on Matrix Mult...

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International Conference on asic

作者： Bisheng Chen Xiayu Li Jicheng Lu Jun Yu State Key Laboratory of ASIC and System Fudan University Shanghai China Shanghai Fudan Microelectronics Group Co. Ltd Shanghai China

As AI begins to face more complex application scenarios, such as intelligent radar, autopilot and intelligent 5G, it often needs to work together with other traditional algorithms, mainly Digital Signal Processing (DSP) algorithms now. The proposed heterogeneous architecture with an AI core (on asic, for CNN) and IP core (on FPGA, for DSP) is usually adopted, but that’s inefficient due to the inconsistency in data transmission and operating frequency between chips. In order to solve this problem, this paper has proposed a reusable architecture based on Matrix Multiplication, which supports convolution, FFT and FIR operations on asic. We first analyzed the relationship among Convolution, FFT and FIR and find the best reusable architecture is Matrix multiplication. Then we decomposed the Convolution, FFT and FIR into Matrix multiplication, and designed the hardware architecture for them. Finally, we used Image registration algorithm to test the performance of our architecture, and get 500% speed up.

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Next-generation machine vision systems incorporating two-dimensional materials: Progress and perspectives

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InfoMat 2022年第1期4卷 23-39页

作者： Peisong Wu Ting He He Zhu Yang Wang Qing Li Zhen Wang Xiao Fu Fang Wang Peng Wang Chongxin Shan Zhiyong Fan Lei Liao Peng Zhou Weida Hu State Key Laboratory of Infrared Physics Shanghai Institute of Technical PhysicsChinese Academy of SciencesShanghaiChina University of Chinese Academy of Sciences BeijingChina Hangzhou Institute for Advanced Study University of Chinese Academy of SciencesHangzhouChina State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghaiChina Henan Key Laboratory of Diamond Optoelectronic Materials and Devices School of Physics and EngineeringZhengzhou UniversityZhengzhouChina Department of Electronic and Computer Engineering The Hong Kong University of Science and TechnologyClear Water BayKowloonHong Kong SARChina School of Physics and Electronics Hunan UniversityChangshaChina

Machine vision systems(MVSs)are an important component of intelligent systems,such as autonomous vehicles and ***,with the continuous increase in data and new application scenarios,new requirements are put forward for the next generation of *** is an urgent need to find new material systems to complement the existing semiconductor technology based on thin-film materials,and new architectures must be explored to improve *** of their unique physical properties,two-dimensional(2D)materials have received extensive attention for use in MVSs,especially in biomimetic ones:the human visual system,which can process complex visual information with low power consumption,provides a model for next-generation *** review paper summarizes the progress and challenges of applying 2D material photodetectors in sense-memory-computational integration and biomimetic image sensors for machine vision.

关键词： in-sensor computing machine vision systems photodetectors two-dimensional materials

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High responsivity and flexible deep-UV phototransistor based on Ta-doped β-Ga_(2)O_(3)

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npj Flexible Electronics 2022年第1期6卷 457-465页

作者： Xiao-Xi Li Guang Zeng Yu-Chun Li Hao Zhang Zhi-Gang Ji Ying-Guo Yang Man Luo Wei-Da Hu David Wei Zhang Hong-Liang Lu State Key Laboratory of ASIC and System Shanghai Institute of Intelligent Electronics&SystemsSchool of MicroelectronicsFudan University200433 ShanghaiChina National Key Laboratory of Science and Technology on Micro/Nano Fabrication Shanghai Jiao Tong University200240 ShanghaiChina Shanghai Synchrotron Radiation Facility(SSRF) Zhangjiang LabShanghai Advanced Research Institute&Shanghai Institute of Applied PhysicsChinese Academy of Sciences201204 ShanghaiChina State Key Laboratory of Infrared Physics Shanghai Institute of Technical PhysicsChinese Academy of Sciences200083 ShanghaiChina

Deep-ultraviolet(DUV)phototransistors have shown great potential applications in UV imaging,artificial intelligence,and wearable *** a large number of wide bandgap semiconductors,the quasi-two-dimensionalβ-Ga_(2)O_(3) is considered as an ideal candidate for DUV photodetector ***,we report a high responsivity(R)and fully flexible Ta-dopedβ-Ga_(2)O_(3) DUV phototransistor which exhibits outstanding optoelectrical properties with a high R of 1.32×10^(6) A/W,a large detectivity of 5.68×10^(14) Jones,a great photo-to-dark current ratio of 1.10×10^(10)%,a high external quantum efficiency of 6.60×10^(8)%,and an ultra-fast response time of~3.50 ***,the flexible Ta-dopedβ-Ga_(2)O_(3) device also displays high reliability and mechanical flexibility that can sustain well after over 1×10^(4) bending ***,high-contrast imaging of UV light was obtained on the flexible DUV detector arrays,which can be efficiently trained and recognized by an artificial neural *** findings offer a perspective to develop wearable optoelectronics and UV imaging based on high-performance flexibleβ-Ga_(2)O_(3) DUV phototransistors,providing an inspiration for the future work in artificial intelligence and bionic robot fields.

关键词： transistor responsivity artificial

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A General-Purpose Compiler Design for Instruction-Based AI Accelerator Implementation

A General-Purpose Compiler Design for Instruction-Based AI A...

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International Conference on asic

作者： Mengxuan Wang Yuan Linghu Chang Wu State Key Laboratory of ASIC and System Fudan University Shanghai China Shanghai Fudan Microelectronics Group Co. Ltd. Shanghai China

With the rapid advancement of deep neural networks, the automatic generation of accelerator design is a very important problem for the deployment of AI applications, especially for edge computation. In this paper, we propose a general purpose compiler design for instruction-based CNN accelerator design. Our compiler incorporates network pruning and quantization capabilities for better performance. CDFG-based layer fusion and scheduling are used for heterogeneous computing with consideration of data transformation and synchronization between CPU and accelerator. A device file is used to define the instruction set and data space so that our compiler supports various accelerator designs uniformly. We used our compiler to implement VGG16 and yolo2 in FPGAs and achieved better performance than existing designs.

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Ultra-thin Body Buried In0.35Ga0.65As Channel MOSFETs with Extremely Low Off-current on Si Substrates

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Chinese Journal of Electronics 2021年第6期30卷 1017-1021页

作者： WANG Bo DING Peng FENG Ruize WANG Yanfu LIU Xiaoyu SUN Tangyou CHEN Yonghe LIU Xingpeng LI Qi LI Yue LIU Yingbo YIN Yihui ZHAO Hao ZHANG Wei LI Haiou JIN Zhi Guangxi Key Laboratory of Precision Navigation Technology and Application Guilin University of Electronic Technology High-Frequency High-Voltage Device and Integrated Circuits Center Institute of MicroelectronicsChinese Academy of Sciences The 34th Research Institute of China Electronics Technology Group Corporation State Key Laboratory of ASIC & System Fudan University

In this paper, we investigated the electrical properties of the Metal-oxide-semiconductor gate stack of Ti/Al2O3/In P under different annealing conditions. A minimum interface trap density of 3×1011cm-2eV-1is obtained without postmetallization annealing ***, utilizing Ti/Al2O3/In P MOS gate stack,we fabricated ultra-thin body buried In0.35 Ga0.65 As channel MOSFETs on Si substrates with optimized on/off trade-off. The 200 nm gate length device with extremely low off-current of 0.6 n A/μm, and on-off ratio of 3.3×10～5, is demonstrated by employing buried low indium(In0.35Ga0.65As) channel with In P barrier/spacer device structure, giving strong potential for future highperformance and low-power applications.

关键词： silicon gallium arsenide Si substrates size 200.0 nm minimum interface trap density III-V semiconductors As extremely low off-current postmetallization annealing treatment Si Ga In ultra-thin body optimized on-off trade-off MOSFET metal-oxide-semiconductor gate stack InP barrier-spacer device structure annealing elemental semiconductors O aluminium compounds different annealing conditions ultra-thin body buried channel MOSFET Ti-Al indium compounds interface states gate length device -InP

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Recent progress in devices and circuits based on wafer-scale transition metal dichalcogenides

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Science China(Information Sciences) 2019年第12期62卷 55-73页

作者： Hongwei TANG Haima ZHANG Xinyu CHEN Yin WANG Xinzhi ZHANG Puyang CAI Wenzhong BAO State Key Laboratory of ASIC and System School of Microelectronics Fudan University

Two-dimensional layered materials(2 DLMs) have triggered a broad research thrust over the last decade worldwide. Different from the gapless graphene, transition metal dichalcogenides(TMDs) exhibit versatile bandstructure, with bandgap sizes ranging from semi-metallic to over 2 e V. Therefore, 2 D-TMDs can be utilized in various applications from logic to optoelectronic devices. In this review we first introduce the latest developments of the wafer-scale synthesis of continuous TMD films, then we present recent advances in large scale devices and circuits based on TMD films, including logic, memory, optoelectronic and analog devices. We also provide a perspective and a look at the future device applications based on wafer-scale2 D-TMDs.

关键词： two-dimensional layered materials transition metal dichalcogenides field effect transistors wafer-scale

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