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A Machine-Learning-Resistant 3D PUF with 8-layer Stacking Vertical RRAM and 0.014% Bit Error Rate Using In-Cell Stabilization Scheme for IoT Security Applications

A Machine-Learning-Resistant 3D PUF with 8-layer Stacking Ve...

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International Electron Devices Meeting (IEDM)

作者： Jianguo Yang Dengyun Lei Deyang Chen Jing Li Haijun Jiang Qingting Ding Qing Luo Xiaoyong Xue Hangbing Lv Xiaoyang Zeng Ming Liu Zhejiang Lab Hangzhou China Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of the Chinese Academy of Sciences Beijing China The No.5 Electronics Research Institute of the Ministry of Industry and Information Technology Guangzhou China State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9781728188881

ISBN: (纸本)9781728188898

In this work, we propose and demonstrate a multi-layer 3-dimensional (3D) vertical RRAM (VRRAM) PUF with in-cell stabilization scheme to improve both cost efficiency and reliability. An 8-layer VRRAM array was manufactured with excellent uniformity and good endurance of >10 7 . Apart from the variation in RRAM resistance, enhanced randomness is obtained thanks to the parasitic IR drop and abundant sneak current paths in 3D VRRAM. To deal with the common issue of unstable bits in PUF output, in-cell stabilization is proposed by first employing asymmetric biasing to detect the unstable bits and then exploiting reprogramming to expand the deviation to stabilize the output. The bit error rate is reduced by >7X (68X) for 3(5) times reprogramming. The proposed PUF features excellent resistance against machine learning attack and passes both National Institute of Standards and Technology (NIST) 800-22 and NIST 800-90B test suites.

关键词： Training Temperature measurement Three-dimensional displays NIST Tin Reliability Testing

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Design of GaN SBD with high cutoff frequency for THz mixer applications

Micro and Nanostructures

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Micro and Nanostructures 2025年 206卷

作者： Siyuan Zhang Xiaolin Hao Guodong Gu Hao Yu Xubo Song Yuanjie Lv Wei Huang D.W. Zhang Junyan Zhu Yanwen Zhang Xiaodong Yang Zhihong Feng State Key Laboratory of ASIC and System Shanghai Institute of Intelligent Electronics & Systems College of Integrated Circuits and Micro-Nano Electronics Fudan University Shanghai 200433 China The National Key Laboratory of Solid-State Microwave Devices and Circuits Hebei Semiconductor Research Institute Hebei Shijiazhuang 050051 China School of Integrated Circuit Jiangnan University Wuxi 214401 China

This work firstly reports the high-frequency GaN planar Schottky barrier diodes (SBDs) for 220 GHz mixer applications, while conducting a systematic investigation into the design and optimization of device frequency performance through advanced device-level simulations. To enhance the cutoff frequency characteristics, device-level Sentaurus-TCAD simulation were employed to establish the quantitative relationship between critical structural parameters (N-GaN layer thickness and anode size) and key electrical parameters (series resistance R s and zero-bias junction capacitance C j0 ). Results reveal that the reduction of the N-GaN layer thickness combined with optimal anode size enables significant improvement in cutoff frequency, achieving theoretical values nearly 4 THz. Guided by these simulations, the device fabricated within current fabrication capabilities achieved a 31.55 Ω R and 2.1 fF C j0 with a 50 nm N-GaN layer thickness and a 0.5 μm anode radius, producing a high cutoff frequency of 2.41 THz. Finally, the SBD fabricated based on simulation was embedded in a quartz based microstrip circuit for testing. The mixer exhibits good millimeter-wave performance with a conversion loss (CL) below 18 dB across 210–224 GHz and an input 1 dB compression point ( P in1dB ) of 2 dBm at room temperature, confirming excellent linearity characteristics. This work establishes following advancements, including the development of a TCAD-based simulation framework for optimizing parasitic parameters and cutoff frequency in GaN SBDs, and the demonstration of high-frequency GaN SBDs’ potential in terahertz mixer systems, providing a novel methodology for advancing GaN technology in terahertz applications.

关键词： Mixers (machinery)

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A Mixed-Variable Bayesian Optimization Approach for Analog Circuit Synthesis

A Mixed-Variable Bayesian Optimization Approach for Analog C...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Jialin Lu Shuhan Zhang Fan Yang Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A.

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

Bayesian Optimization (BO) is an efficient method for black-box optimization problems. It has been successfully applied to the analog circuit sizing problem. However, all the design variables are viewed as continuous variables in these methods. Actually, many design variables are discrete due to the design rules. In this paper, we proposed an improved BO method for analog circuit sizing with both discrete and continuous variables. We also utilize the Gaussian Process (GP) regression model as the surrogate model for BO. However, we modified the kernel of GP and make it applicable to mixed variables. Experimental results demonstrated that the proposed mixed-variable BO method can significantly reduce the number of simulations with comparable optimization results, compared with the existing BO methods.

关键词： Optimization Analog circuits Kernel Linear programming Bayes methods Integrated circuit modeling Gaussian processes

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Dense-Atrous U-Net with salient computing for Accurate Retina Vessel Segmentation

Dense-Atrous U-Net with salient computing for Accurate Retin...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Xiao-Min Li Geng-Sheng Chen Shu-Yang Wang State Key Laboratory of ASIC and System Fudan University Shanghai China School of Basic Medical Sciences Fudan University Shanghai China

ISBN: (数字)9781728162355

ISBN: (纸本)9781728162362

Retina vessel segmentation is a fundamental step in the diagnosis of diabetic retinopathy. U-Net is one of the most popular methods for medical image segmentation. However, the consecutive pooling and convolution operations lead to the loss of spatial information. In this paper, we propose a densely connected U-Net with parallel atrous convolution block and salient computing block, which is named DAS-UNet. There are several advantages of DAS-UNet for vessel segmentation. First, the dense connectivity strengthen feature propagation. Second, the parallel atrous convolution block (PAC Block) employs different receptive fields to generate more abstract features for accurate segmentation. Third, we can highlight responsive region and suppress irrelevant regions through salient computing block (SCB), which allows us to obtain a clear vessel segmentation map than the U-Net. Comprehensive experiments on DRIVE benchmark indicates that DAS-UNet achieves a state-of-the-art performance with a significantly clear result.

关键词： Convolution Image segmentation Picture archiving and communication systems Feature extraction Medical diagnostic imaging Computational modeling Sensitivity

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Investigations on the resistance reduction effect of double-trench sic mosfets under repetitive avalanche stress 18th

Investigations on the resistance reduction effect of double-...

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18th International Conference on Silicon Carbide and Related Materials, ICSCRM 2019

作者： Wei, Jiaxing Liu, Siyang Li, Sheng Tang, Lizhi Lou, Rongcheng Fu, Hao Zhao, Hangbo Sun, Weifeng Zhang, Xiaobing Bai, Song National ASIC System Engineering Research Center School of Electronics Science and Engineering Southeast University China Display R&D Center School of Electronics Science and Engineering Southeast University China State Key Laboratory of Wide-bandgap Semiconductor Power Electronic Devices Nanjing Electronic Device Institute China

ISBN: (纸本)9783035715798

The unexpected resistance reduction effect of double-trench SiC MOSFETs under repetitive avalanche stress is investigated in this work. After enduring repetitive avalanche stress, the ON-state drain-source resistance (Rdson) of the device decreases. With the help of TCAD simulations, the dominant mechanism is proved to be the injection of positive charges into the gate trench bottom oxide, which is almost irreversible under zero-voltage bias condition at room temperature. For the injected positive charges attract extra electrons just beneath the gate trench bottom, where the carriers pass through under ON state, the resistivity there is reduced, improving the conduction capability of the device. Moreover, an optimization method is proposed. Since the impact ionization rate (I.I.) and the vertical oxide electric field (E⊥) along the gate trench bottom oxide interface contribute to the injection of positive charges, it is recommended to make the bottom oxide thicker to suppress this effect. © 2020 Trans Tech Publications Ltd, Switzerland.

关键词： Impact ionization

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A Comparator-Reused Dynamic-Amplifier for Noise-Shaping SAR ADC

A Comparator-Reused Dynamic-Amplifier for Noise-Shaping SAR ...

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International Conference on asic

作者： Longheng Luo Xingchen Shen Jianguo Diao Fan Ye Junyan Ren State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

This paper presents a high-speed high-gain dynamic amplifier which can also be reused as a comparator for a noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC). By modifying a strong-arm latch, this dynamic amplifier can achieve a high speed of comparison and dynamic amplification, which is crucial to a high-performance NS SAR ADC. The prototype is designed in 28 nm CMOS process. It realizes the comparison speed of 0.2 ns and 8 times dynamic amplification in 0.9 ns with 0.6 pF single-end capacitance load. Meanwhile, the noise floor is 11 nV/√Hz and the THD is -76.5 dB with the power consumption of 56 μW averagely.

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A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis

A Hardware-efficient Accelerator for Encoding Stage of Text-...

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International Conference on asic

作者： Riyong Zheng Chenghao Wang Jun Han Xiaoyang Zeng School of Microelectronics Fudan University Shanghai China State Key Laboratory of ASIC and System

Text-to-speech synthesis is a promising human- computer interaction technology. Google launched the TTS model Tacotron, which can directly convert raw text to speech. The encoder module is one of the most important components of Tacotron. It extracts context features in the text and generate time series. The encoder module contains Recurrent Neural Network (RNN) and Convolutional Neural Network (CNN). There are few hardware accelerators to support these hybrid algorithm and the parallel architecture calculations. To this end, we designed a hardware-efficient accelerator to accomplish the complex computing tasks. We quantify the network model to reduce hardware overhead while using parallel hardware structures to increase operating speed. The encoder accelerator can process 2903 bits data per second with 3.627W. Compared to Titan X, the energy efficiency ratio is 71 times higher.

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Novel Semiconductor devices Based on SOL Substrate

Novel Semiconductor devices Based on SOL Substrate

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China Semiconductor Technology International Conference (CSTIC)

作者： K. Xiao J. Liu JN. Deng YL. Jiang WZ. Bao A. Zaslavsky S. Cristoloveanu X. Gong J. Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China State key lab of ASIC and System School of Microelectronics Fudan University Shanghai China Brown University Providence RI USA IMEP-LAHC INP-Grenoble/Minatec Grenoble France National University of Singapore (NUS) Singapore

ISBN: (数字)9781728165585

ISBN: (纸本)9781728165592

In this work, we review our recent studies on several novel devices built on silicon-on-insulator (SOI) substrates. The sharp-switching Z2- FET , based on a feedback mechanism, has been demonstrated as suitable for many applications. The PISD, capable of in-situ photoelectron sensing, has been used as a one-transistor active pixel sensor (1T-APS). Furthermore, an SOI/MoS 2 heterojunction FET has been demonstrated as both a photodetector with a dynamic response spectrum and as a novel one-transistor wavelength detector (1T-WD) with an output signal sensitive to the variation of wavelength rather than intensity.

关键词： Semiconductor devices Silicon-on-insulator Heterojunctions Sensors Sulfur Substrates Physics

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Resistive Memory-based Neural Differential Equation Solver for Score-based Diffusion Model

arXiv

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arXiv 2024年

作者： Yang, Jichang Chen, Hegan Chen, Jia Wang, Songqi Wang, Shaocong Yu, Yifei Chen, Xi Wang, Bo Zhang, Xinyuan Cui, Binbin Li, Yi Lin, Ning Xu, Meng Li, Yi Xu, Xiaoxin Qi, Xiaojuan Wang, Zhongrui Zhang, Xumeng Shang, Dashan Wang, Han Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering the University of Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200433 China Institute of the Mind the University of Hong Kong Hong Kong University of Chinese Academy of Sciences Beijing100049 China School of Integrated Circuits Hubei Key Laboratory for Advanced Memories Huazhong University of Science and Technology Wuhan430074 China Department of Electronic and Computer Engineering the Hong Kong University of Science and Technology Hong Kong

Human brains image complicated scenes when reading a novel. Replicating this imagination is one of the ultimate goals of AI-Generated Content (AIGC). However, current AIGC methods, such as score-based diffusion, are still deficient in terms of rapidity and efficiency. This deficiency is rooted in the difference between the brain and digital computers. Digital computers have physically separated storage and processing units, resulting in frequent data transfers during iterative calculations, incurring large time and energy overheads. This issue is further intensified by the conversion of inherently continuous and analog generation dynamics, which can be formulated by neural differential equations, into discrete and digital operations. Inspired by the brain, we propose a time-continuous and analog in-memory neural differential equation solver for score-based diffusion, employing emerging resistive memory. The integration of storage and computation within resistive memory synapses surmount the von Neumann bottleneck, benefiting the generative speed and energy efficiency. The closed-loop feedback integrator is time-continuous, analog, and compact, physically implementing an infinite-depth neural network. Moreover, the software-hardware co-design is intrinsically robust to analog noise. We experimentally validate our solution with 180 nm resistive memory in-memory computing macros. Demonstrating equivalent generative quality to the software baseline, our system achieved remarkable enhancements in generative speed for both unconditional and conditional generation tasks, by factors of 64.8 and 156.5, respectively. Moreover, it accomplished reductions in energy consumption by factors of 5.2 and 4.1. Our approach heralds a new horizon for hardware solutions in edge computing for generative AI applications. © 2024, CC BY-NC-SA.

关键词： Diffusion

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Dual-Loop-Controlled AC-Coupling 100MHz Bandwidth Envelope Tracking Modulator for 5G RF Power Amplifier

Dual-Loop-Controlled AC-Coupling 100MHz Bandwidth Envelope T...

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International Conference on asic

作者： Fuqiang Liu Mingfeng Chen Heng Ma Zhiliang Hong State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

A dual-loop-controlled ac-coupling envelope tracking modulator (ETM) with 100MHz bandwidth is presented. Ac-coupling voltage Voff_AC is stabilized by voltage sensor and the control pulse width can be automatically widened (AWPW), meanwhile an auxiliary automatically widen pulse width (AAWPW) technique is proposed to control ripple voltage. AWPW and AAWPW can significantly reduce switching loss by filtering high switching frequency, leading to overall efficiency improvement. The maximum output power exceeds 2W with a constant load 6Ω//600pF, maximum ac amplitude is 3V, peak efficiency is 85%.

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