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arXiv 2020年

作者： Chen, Xiaojing Lu, Zhouyu Ni, Wei Wang, Xin Wang, Feng Zhang, Shunqing Xu, Shugong Shanghai Institute for Advanced Communication and Data Science Shanghai University Shanghai200444 China SydneyNSW2122 Australia State Key Laboratory of ASIC and System Shanghai Institute for Advanced Communication and Data Science Department of Communication Science and Engineering Fudan University Shanghai200433 China School of Information Engineering Guangdong University of Technology Guangzhou510006 China

Driven by explosive computation demands of Internet of Things (IoT), mobile edge computing (MEC) provides a promising technique to enhance the computation capability for mobile users. In this paper, we propose a joint resource allocation and load management mechanism in an MEC system with wireless power transfer (WPT), by jointly optimizing the transmit power for WPT, the local/edge computing load, the offloading time, and the frequencies of the central processing units (CPUs) at the access point (AP) and the users. To achieve an energy-efficient and sustainable WPT-MEC system, we minimize the total energy consumption of the AP, while meeting computation latency requirements. Cooling energy which is non-negligible, is taken into account in minimizing the energy consumption of the MEC system. By rigorously orchestrating the state-of-the-art optimization techniques, we design an iterative algorithm and obtain the optimal solution in a semi-closed form. Based on the solution, interesting properties and insights are summarized. Extensive numerical tests show that the proposed algorithm can save up to 90.4% the energy of existing benchmarks. Copyright © 2020, The Authors. All rights reserved.

关键词： Convex optimization

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Front Cover: A Strain-engineered Helical Structure as a Self-adaptive Magnetic Microswimmer (ChemNanoMat 6/2021)

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ChemNanoMat 2021年第6期7卷

作者： Xiaojie Shi Jinrun Liu Ye Kong Dr. Borui Xu Prof. Tianlong Li Prof. Alexander A. Solovev Prof. Yongfeng Mei Department of Materials Science & State Key Laboratory of ASIC and Systems Fudan University 220 Handan Road Shanghai 200433 P. R. China School of Mechatronics Engineering & State Key Laboratory of Robotics and System Harbin Institute of Technology 92 Xi Da Zhi Jie Haerbin 150001 P. R. China

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Hybrid Preconditioned CG Detection with Sequential Update for Massive MIMO systems

Hybrid Preconditioned CG Detection with Sequential Update fo...

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IEEE Workshop on Signal Processing systems (SIPS)

作者： Jing Zeng Jun Lin Zhongfeng Wang Yun Chen School of Electronic Science and Engineering Nanjing University P. R. China ASIC and System State Key Laboratory Fudan University P. R. China

ISBN: (数字)9781728119274

ISBN: (纸本)9781728119281

Massive Multi-Input Multi-Output (MIMO) is one of the key technologies for the fifth generation communication systems. Conjugate Gradient (CG) algorithm approximates the minimum mean-square error (MMSE) in an iterative manner, which avoids full matrix inversion. Pre-conditioned CG (PCG) was presented to improve the robustness of CG method. However, for the PCG, a sparse matrix inversion is still required in preprocessing and the performance is only comparable to MMSE. In this paper, a hybrid PCG algorithm (HPCG) with sequential update is proposed with superior performance and low complexity. The preconditioned matrix is replaced by a diagonal matrix by exploring its characteristics, which avoids matrix inversion and incomplete Cholesky factorization. Besides, to improve the bit error performance, a sequential update strategy is employed for estimated signals after PCG detection. For a MIMO system with 128 receive antennas, simulation results show the proposed HPCG algorithm outperforms MMSE by 0.25 dB to 1.5 dB under different numbers of users. Based on the channel hardening theories, several signal vectors can be transmitted in the same channel condition. When 10 signal vectors are considered, compared to the other CG based algorithms, the overall complexity of HPCG can be reduced by 3.9% to 56%.

关键词： Bit error rate Sparse matrices MIMO communication Complexity theory Approximation algorithms Jacobian matrices Robustness

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Thickness-Dependent Electronic Transport in Ultrathin, Single Crystalline Silicon Nanomembranes (vol 5, 1900232, 2019)

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ADVANCED ELECTRONIC MATERIALS 2019年第12期5卷

作者： Song, Enming Guo, Zhongxun Li, Guodong Liao, Fuyou Li, Gongjin Du, Haina Schmidt, Oliver G. Kim, Minju Yi, Yeonjin Bao, Wenzhong Mei, Yongfeng Department of Materials Science State Key Laboratory of ASIC and Systems Fudan University Shanghai 200433 P. R. China Department of Materials Science and Engineering Frederick Seitz Materials Research Laboratory University of Illinois at Urbana-Champaign Urbana IL 61801 USA Center for Bio-Integrated Electronics Northwestern University Evanston IL 60208 USA School of Microelectronics State Key Laboratory of ASIC and System Fudan University Shanghai 200433 P. R. China Material Systems for Nanoelectronics Chemnitz University of Technology Chemnitz 09107 Germany Department of Physics Yonsei University Seoul 03722 Republic of Korea

As distinct from bulk silicon, ultrathin silicon-on-insulator (SOI) or silicon nanomembranes (Si-NMs) offer excellent electronic and mechanical properties that are essential to the development of electronic/optoelectronic systems. Ultrathin Si-NM field effect transistors (FETs) based on p-doped SOI (100) wafers are investigated. The thickness of the Si-NMs is controllably reduced from 50 nm to 10 nm through the use of a unique etching process. Based on systematic investigation of Si-NM FETs with varying thicknesses, both insulating and metallic behaviors are observed, which can be attributed to carrier enhancement by surface-dipole doping after thickness reduction. Spectroscopy characterization and theoretical simulations reveal that this high surface-dipole density can be inverted, yielding high-density electrons regardless of the bulk p-doped nature of the material, thus significantly enhancing its conductivity. These findings offer a physical understanding of thickness dependence, which is critical to the future development of ultrathin SOI electronics, of relevance to a diverse range of semiconductor applications.

关键词： insulator-to-metal transition silicon nanomembrane surface dipole density temperature dependence ultrathin thickness

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Infrared Photodetectors: Extrinsic Photoconduction Induced Short-Wavelength Infrared Photodetectors Based on Ge-Based Chalcogenides (Small 4/2021)

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Small 2021年第4期17卷

作者： Ting He Zhen Wang Ruyue Cao Qing Li Meng Peng Runzhang Xie Yan Huang Yang Wang Jiafu Ye Peisong Wu Fang Zhong Tengfei Xu Hailu Wang Zhuangzhuang Cui Qinghua Zhang Lin Gu Hui-Xiong Deng He Zhu Chongxin Shan Zhongming Wei Weida Hu State Key Laboratory of Infrared Physics Shanghai Institute of Technical Physics Chinese Academy of Sciences 500 Yutian Road Shanghai 200083 China School of Electronic Electrical and Communication Engineering University of Chinese Academy of Sciences Beijing 100049 China State Key Laboratory of Superlattices and Microstructures Institute of Semiconductors Chinese Academy of Sciences Beijing 100083 China Hangzhou Institute for Advanced Study University of Chinese Academy of Sciences Hangzhou 310024 China State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai 200433 China Beijing National Laboratory for Condensed Matter Physics Institute of Physics Chinese Academy of Sciences Beijing 100190 China Henan Key Laboratory of Diamond Optoelectronic Materials and Devices School of Physics and Engineering Zhengzhou University Zhengzhou 450001 China

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High-performance logic and memory devices based on a dual-gated MoS2 architecture

arXiv

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arXiv 2019年

作者： Liao, Fuyou Guo, Zhongxun Wang, Yin Xie, Yufeng Zhang, Simeng Sheng, Yaochen Tang, Hongwei Xu, Zihan Riaud, Antoine Zhou, Peng Wan, Jing Fuhrer, Michael S. Jiang, Xiangwei Zhang, David Wei Chai, Yang Bao, Wenzhong State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai200433 China Department of Applied Physics Hong Kong Polytechnic University Hong Kong State Key Laboratory of ASIC and System School of Information Science and Engineering Fudan University Shanghai200433 China ARC Centre of Excellence in Future Low-Energy Electronics Monash University VIC3800 Australia School of Physics and Astronomy Monash University VIC3800 Australia Institute of Semiconductors Chinese Academy of Sciences Beijing100083 China Six Carbon Tech. Shenzhen Shenzhen518106 China

In this work, we demonstrate a dual-gated (DG) MoS2 field effect transistors (FETs) in which the degraded switching performance of multilayer MoS2 can be compensated by the DG structure. It produces large current density (>100 μA/μm for a monolayer), steep subthreshold swing (SS) (~100 mV/dec for 5 nm thickness), and high on/off current ratio (greater than 107 for 10 nm thickness). Such DG structure not only improves electrostatic control but also provides an extra degree of freedom for manipulating the threshold voltage (VTH) and SS by separately tuning the top and back gate voltages, which are demonstrated in a logic inverter. Dynamic random access memory (DRAM) has a short retention time because of large OFF-state current in the Si MOSFET. Based on our DG MoS2-FETs, and a DRAM unit cell with a long retention time of 1260 ms are realized. A large-scale isolated MoS2 DG-FETs based on CVD-synthesized continuous films is also demonstrated, which shows potential applications for future wafer-scale digital and low-power electronics. Copyright © 2019, The Authors. All rights reserved.

关键词： Degrees of freedom (mechanics)

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Erratum to: Large circuit models: opportunities and challenges

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SCIENCE CHINA Information Sciences 2024年第11期67卷 1-1页

作者： Lei CHEN Yiqi CHEN Zhufei CHU Wenji FANG Tsung-Yi HO Ru HUANG Yu HUANG Sadaf KHAN Min LI Xingquan LI Yu LI Yun LIANG Jinwei LIU Yi LIU Yibo LIN Guojie LUO Hongyang PAN Zhengyuan SHI Guangyu SUN Dimitrios TSARAS Runsheng WANG Ziyi WANG Xinming WEI Zhiyao XIE Qiang XU Chenhao XUE Junchi YAN Jun YANG Bei YU Mingxuan YUAN Evangeline F.Y. YOUNG Xuan ZENG Haoyi ZHANG Zuodong ZHANG Yuxiang ZHAO Hui-Ling ZHEN Ziyang ZHENG Binwu ZHU Keren ZHU Sunan ZOU Huawei Noah's Ark Lab Hong Kong 999077 China School of Integrated Circuits Peking University Beijing 100871 China Faculty of Electrical Engineering and Computer Science Ningbo University Ningbo 315211 China Department of Electronic and Computer Engineering Hong Kong University of Science and Technology Hong Kong 999077 China Department of Computer Science and Engineering The Chinese University of Hong Kong Hong Kong 999077 China School of Integrated Circuits Southeast University Nanjing 210096 China Huawei HiSilicon Shenzhen 518129 China Peng Cheng Laboratory Shenzhen 518052 China School of Computer Science Peking University Beijing 100871 China School of Microelectronics State Key Laboratory of Integrated Chips and System Fudan University Shanghai 200433 China School of Artificial Intelligence Shanghai Jiao Tong University Shanghai 200240 China

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A Low-Noise 56Gbps PAM-4 Linear Optical Receiver in 40nm CMOS

A Low-Noise 56Gbps PAM-4 Linear Optical Receiver in 40nm CMO...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Ting-Yu Yao Dan Li Yang Xie Patrick Yin Chiang Zhi-Liang Hong State Key Laboratory of ASIC & System Fudan University Shanghai China School of Microelectronics Xi’an Jiaotong University Xi’an China

A 56Gb/s PAM-4 low-noise linear optical receiver is presented. To reduce the input referred noise (IRN) and improve the sensitivity, the optical receiver front-end comprises of a high-gain narrow-bandwidth transimpedance amplifier (TIA) followed by a two-stage equalizer. The gain tunable TIA and the variable gain amplifier (VGA) with automatic gain control (AGC) loop ensure the linearity across the whole input range. Designed and implemented in 40nm CMOS technology, the receiver accomplishes 1.7μArms IRN, 78dBΩ transimpedance gain and 23GHz bandwidth while consuming 108mW from 1.6V supply. The dynamic range of transimpedance is 40dB, enabling large input overload current of 2.5mA pp and total harmonica distortion (THD) is below 3% with 800mV pp swing at the output.

关键词： Optical receivers Gain control Bandwidth Linearity Gain CMOS technology

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A Proved Dither-injection Method for Memory Effect in Double Sampling Pipelined ADC 12

A Proved Dither-injection Method for Memory Effect in Double...

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2017 IEEE 12th International Conference on asic

作者： Fubiao Cao Yongzhen Chen Yuefeng Cao Fan Ye Junyan Ren State Key Laboratory of ASIC and System(Fudan University) Department of Microelectronics Fudan University

ISBN: (纸本)9781509066261;9781509066254

Double sampling pipelined ADC is solution for high speed ADC besides TI ***,memory effect is introduced for lack of the reset phase between two ***-injection method is a choice for calibrating the memory effect but it has to balance the accuracy of the output with the convergence *** paper presents a different transfer curve model to reduce the convergence *** method is realized using a LMS algorithm to calibrate memory effect and incomplete settling *** in MATLAB shows a 12 bit pipelined ADC can converge in 10～5 cycle and achieve 87.87 d Bc SFDR and 10.7 bit ENOB.

关键词： A Proved Dither-injection Method for Memory Effect in Double Sampling Pipelined ADC LMS

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An input buffer for 12bit 2GS/s ADC 12

An input buffer for 12bit 2GS/s ADC

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2017 IEEE 12th International Conference on asic

作者： Fubiao Cao Yongzhen Chen Zhiyuan Dai Fan Ye Junyan Ren State Key Laboratory of ASIC and System(Fudan University) Department of Microelectronics Fudan University

ISBN: (纸本)9781509066261;9781509066254

An input buffer using in 2 GS/s 12 bit resolution analog-to-digital converter(ADC) is presented in this *** input buffer is often used in the ADC application to isolate the input *** of the most important design tasks of the input buffer is to suppress the non-linearity introduced by the extracted or absorbed current in the sampling *** this design,a wide-band input buffer is based on the one-stage source follower structure and improved by using extra capacitors and MOS devices to suppress the non-linear *** is supplied by the LDOs for the extra MOS devices to ensure its linear dynamic *** consumes 70.1 m W power in 2 GHz sampling rate and 68.14 d B SFDR at 1 GHz input frequency in post simulation.

关键词： MOS An input buffer for 12bit 2GS/s ADC

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