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25th International Conference on Field Programmable Logic and Applications, FPL 2015

作者： Jian, Yan Jifang, Jin Wang, Ying Zhou, Xuegong Leong, Philip Lingli, Wang State Key Laboratory of ASIC and System Fudan University No. 825 Zhangheng Road Shanghai China School of Electrical and Information Engineering University of Sydney Room 852 Electrical Engineering Building J03 Australia

ISBN: (纸本)9780993428005

This paper proposes UniStream, a unified stream architecture based on point-To-point stream channels combining both bitstream configuration and data stream processing. In addition, unified APIs are provided to support bitstream configuration and data stream processing, as well as the stream interconnect. A cost model is also presented for the overhead on the stream interconnect, hardware task configuration and data stream processing at system level, which can be used during the early stage of development. The flexibility and high efficiency of UniStream are demonstrated on Xilinx Virtex-5 and Virtex-6 FPGAS. Experimental results on bitstream configuration/read-back, data encryption/decryption and Discrete Cosine Transformation show that performance can be significantly improved with different stream modes. © 2015 Imperial College.

关键词： Cryptography

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Feature-scale Simulations of Particulate Slurry Flows in Chemical Mechanical Polishing by Smoothed Particle Hydrodynamics

Feature-scale Simulations of Particulate Slurry Flows in Che...

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第十七届全国流体力学数值方法研讨会

作者： DongWang Sihong Shao ChanghaoYan Wei Cai Xuan Zeng State Key Laboratory of ASIC and System School ofMicroelectronics Fudan University Shanghai 201203 China State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai 201203 China LMAM and School of Mathematical Sciences Peking University Beijing 100871China Department of Mathematics and Statistics University of North Carolina at CharlotteCharlotte NC 28223 USA

Chemical mechanical polishing (CMP) is a key process widely used in semiconductor manufacturing industry to provide local and global planarity of silicon *** this talk, the mechanisms of material removal in CMP process are investigated in detail by the smoothed particle hydrodynamics (SPH) method where an new, efficient and parallel neighbour search method based on plane sweep algorithm is proposed at the same *** feature-scale behaviours of slurry flow,rough pad, wafer defects, moving solid boundaries, slurry-abrasive interactions and abrasive collisions are modeled and simulated.

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A 20 μW dual-channel analog front-end in 65nm CMOS for portable ECG monitoring system

A 20 μW dual-channel analog front-end in 65nm CMOS for port...

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International Conference on asic

作者： Shuo Li Nan Qi Vahid Behravan Zhiliang Hong Patrick Y. Chiang State Key Laboratory of ASIC & System Fudan University Shanghai China School of EECS Oregon State University Corvallis OR USA

This paper presents a dual-channel analog front-end (AFE) for portable ECG monitoring system. The AFE consists of an instrumentation amplifier, a DC servo loop (DSL), a fixed gain amplifier (FGA), a programmable gain amplifier (PGA) and an ADC buffer. To achieve high input impedance, a DC-coupled current feedback instrumentation amplifier (CFIA) is adopted. Fabricated in 65nm CMOS process, the AEF occupies 0.16mm 2 area and consumes 20μW. Measurement results show that the AFE achieves 2.5GΩ input impedance, 73dB CMRR at 50Hz and 40/53.7dB tunable gain.

关键词： Electrocardiography Impedance Bandwidth Gain DSL Capacitors Voltage measurement

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A 9.8 Gbps, 6.5 mW forwarded-clock receiver with phase interpolator and equalized current sampler in 65 nm CMOS

A 9.8 Gbps, 6.5 mW forwarded-clock receiver with phase inter...

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Microwave, MTT-S International Symposium

作者： Shunli Ma Sai Manoj Hao Yu Junyan Ren Roshan Weerasekera State Key Lab of ASIC and System Fudan University Shanghai China School of EEE Nanyang Technological University Singapore Institute of Microelectronics Singapore

A full-rate energy-efficient forwarded-clock (FC) receiver is demonstrated in this paper. A current sampler with continuous-time equalization is realized with 20 GHz bandwidth in sampling for data recovery. Moreover, a phase interpolator is introduced to generate sampling clock with deskew for data recovery. The testing chip was fabricated in 65 nm CMOS process in area of 0.16 mm 2 . Measurement shows that the FC receiver can achieve a data-rate up to 9.8 Gbps and power consumption is 6.5 mW.

关键词： CMOS integrated circuits Clocks CMOS technology Receivers Oscillators Large scale integration

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CMOS amplifier for neural signal recording applications

CMOS amplifier for neural signal recording applications

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16th Annual Conference and 5th International Conference on Chinese Society of Micro-Nano Technology, CSMNT 2014

作者： Zhang, Zhang Cheng, Zhengxi Zhuang, Yiwei Key Laboratory of Infrared Imaging Materials and Detectors Shanghai Institute of Technical Physics Chinese Academy of Sciences Shanghai China State Key Laboratory of ASIC and System Fudan University Shanghai China School of Electronic Science and Applied Physics Hefei University of Technology Hefei Anhui China

ISBN: (纸本)9783038354628

A low power low noise CMOS amplifier with integrated filter for neural signal recording is designed and fabricated with CSMC 0.5 μm CMOS process. DC offsets introduced by electrode-tissue interface are rejected through a feedback low-pass filter. The bandwidth of the amplifier is in 3.5Hz-5.5KHz range, and the gain is about 48dB in the midband. AC input differential mode voltage range is 10mV, and DC input differential mode voltage range is 180mV. The amplifier can accommodate 180mV DC offsets drift and 10mV neural spikes. The neural probe array is integrated directly on the surface of the amplifier array chip, and is tested in saline solution, and also is implanted in rats in vivo, the results of the experiments show that the amplifier is suitable for neural signal recording. The power dissipation is about 14μW while consuming 0.16 mm2 of chip area, which satisfies implantable devices requirements. © (2015) Trans Tech Publications, Switzerland.

关键词： Signal processing

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UniStream: A unified stream architecture combining configuration and data processing

UniStream: A unified stream architecture combining configura...

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International Conference on Field Programmable Logic and Applications

作者： Jian Yan Jifang Jin Ying Wang Xuegong Zhou Philip Leong Lingli Wang State Key Laboratory of ASIC and System Fudan University Shanghai China School of Electrical and Information Engineering The University of Sydney Australia

This paper proposes UniStream, a unified stream architecture based on point-to-point stream channels combining both bitstream configuration and data stream processing. In addition, unified APIs are provided to support bitstream configuration and data stream processing, as well as the stream interconnect. A cost model is also presented for the overhead on the stream interconnect, hardware task configuration and data stream processing at system level, which can be used during the early stage of development. The flexibility and high efficiency of UniStream are demonstrated on Xilinx Virtex-5 and Virtex-6 FPGAs. Experimental results on bitstream configuration/ read-back, data encryption/decryption and Discrete Cosine Transformation show that performance can be significantly improved with different stream modes.

关键词： Hardware Computer architecture Field programmable gate arrays system-on-chip Throughput Software Data models

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Efficient modeling and implementation of cryptographic processor using UML and systemC

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Journal of Computational Information systems 2015年第10期11卷 3809-3820页

作者： Ma, De Chu, Chaoqiang Li, Chunshu Meng, Jianyi Yan, Xiaolang Institute of Microelectronics CAD Hangzhou Dianzi University Hangzhou China Institute of VLSI Design Zhejiang University Hangzhou China Belgium State Key Laboratory of ASIC and System Fudan University Shanghai China

To mitigate the increasing design complexity of very large scale integrated circuits (VLSI), the abstraction level design engineers work on has to be raised. In this paper, we propose an efficient UML-and systemC-based design flow with performance, area and power coestimation at early stages and apply it to RSA and ECC crypto-Processor implementation. It is divided into several sections. Firstly, the UML class diagram is used to describe the target architecture and the UML sequence and state diagrams are used to describe the dynamic behavior of the design. Secondly, systemC behavior models are translated from the UML models semi-automatically and TLM models are refined from systemC behavior models. During systemC behavior and TLM modeling process, the estimation methodology of performance, power and area is combined to facilitate architecture exploration. This can avoid extensive redesign, reduce cost/time and achieve good trade-off in power, area and performance. Thirdly, a hybrid simulation of TLM and RTL models is proposed to validate the refinement from TLM to RTL. The experimental results with performance, power, and area estimation at different abstraction levels are adopted to demonstrate the efficiency of the proposed design flow for RSA and ECC crypto-processor design. ©, 2015, Binary Information Press. All right reserved.

关键词： Integrated circuit design

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A hybrid integrated TIA and PD for 20-Gb/s optical receivers

A hybrid integrated TIA and PD for 20-Gb/s optical receivers

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OptoElectronics and Communications Conference, OECC

作者： Qianqian Yang Nan Qi Juncheng Wang Zhongkai Wang Zhiliang Hong Patrick Chiang ASIC & System State Key Laboratory Fudan University Shanghai China School of Electrical Engineering and Computer Science Oregon State University Corvallis OR USA

A 20Gb/s Transimpedance Amplifier (TIA) is implemented in 65nm CMOS process using input-serial-peaking technique. Measurement results show that the hybrid integrated TIA with PD achieves up to 20Gb/s clean optical-dia... 详细信息

关键词： Optical variables measurement Optical amplifiers Bandwidth Stimulated emission Optical fibers Optical receivers

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Polarization fatigue in antiferroelectric (Pb,La)(Zr,Ti)O3 thin films: The role of the effective strength of driving waveform

Polarization fatigue in antiferroelectric (Pb,La)(Zr,Ti)O3 t...

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作者： Geng, Wenping Liu, Yang Lou, Xiaojie Zhang, Fuping Liu, Qida Dkhil, Brahim Zhang, Ming Ren, Xiaobing He, Hongliang Jiang, Anquan State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai200433 China Multi-disciplinary Materials Research Center Frontier Institute of Science and Technology State Key Laboratory for Mechanical Behavior of Materials Xi'An Jiaotong University Xi'an710049 China Laboratoire Structures Propriétés et Modélisation des Solides UMR 8580 CNRS-Ecole Centrale Paris Grande Voie des Vignes Châtenay-Malabry-Cedex92295 France National Key Laboratory of Shock Wave and Detonation Physics Institute of Fluid Physics CAEP Mianyang621900 China State Key Laboratory for Strength and Vibration of Mechanical Structures Xi'An Jiaotong University 710049 China

In this study, a critical parameter termed as "effective electric strength" is developed to depict polarization fatigue in antiferroelectric thin films. Specifically, the effect of pulse width, frequency, and magnitude of driving voltage (or field) on polarization fatigue of antiferroelectric (Pb,La)(Zr,Ti)O3 (PLZT) thin films was investigated in detail. By transforming all the waveforms with different pulse-widths/voltages/frequencies into their effective electric strength, a strong correlation between the effective strength and the degree of polarization fatigue in the PLZT films is revealed. For instance, it was found that appreciable fatigue usually occurs when the effective strength is larger than or equal to the voltage of phase transition from antiferroelectric phase to ferroelectric phase. In addition, it is shown that the films are more prone to fatigue for a lower frequency of the same effective strength. Our findings could be well explained in the framework of the local phase decomposition arising from switching induced charge injection. © 2015 Elsevier Ltd and Techna Group S.r.l. All rights reserved.

关键词： Electronic properties

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Differential Power Analysis on Dynamic Password Token Based on SM3 Algorithm, and Countermeasures

Differential Power Analysis on Dynamic Password Token Based ...

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International Conference on Computational Intelligence and Security

作者： Limin Guo Lihui Wang Qing Li Jun Yu Peng Luo Shanghai Fudan Microelectronics Group Co. Ltd State Key Laboratory of ASIC and System Shanghai China Fudan University Shanghai China Commercial Cryptography Testing Center Beijing China

Dynamic password technology is widely utilized for identity authentication, which depends on using hash functions, such as SM3. And SM3 hash algorithm is based on the mixing of different group operations, such as XOR and addition modulo 232. In this paper, we present two original first-order differential power analysis attacks on dynamic password token based on SM3 algorithm. The two proposed DPA attacks are against XOR and addition modulo 232 operation respectively. Experimental results show that dynamic password token based on SM3 algorithm is vulnerable to side channel attacks, no matter implemented in software or hardware. We also provide a masked implementation of the algorithm, which is designed to avoid those proposed attacks.

关键词： Heuristic algorithms Algorithm design and analysis Software algorithms Software Mathematical model Power demand Hardware

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