检索结果-内蒙古大学图书馆

International Conference on Ion Implantation Technology (IIT)

作者： J.B. Liu J. Luo J.F. Li C. Chen G.L. Wang T. Chen T.T. Li J. Zhong D.P. Wu P. Xu C. Zhao Key Laboratory of Microelectronics Devices and Integrated Technology Chinese Academy of Sciences Beijing China State Key Laboratory of ASIC and System Fudan University Shanghai China

The formation of N-type Ge shallow junction is investigated in this work. By combining carbon co-implantation and microwave annealing (MWA) method, the junction depth of 34 nm measured by secondary ion mass spectroscopy (SIMS) as well as sheet resistance of 467 ohm/sq measured by Hall is achieved. Results show that the opitimal carbon implantation energy is 8 keV in that distributed carbon ions at such an energy can effectively trap vacancies and phosphorous into immobile clusters. The recrystallization of amorphous layer after MWA annealing is also studied by both ellipsometry and transmission electron microscopy (TEM).

关键词： Carbon Junctions Germanium Rapid thermal annealing microelectronics Electrical resistance measurement

来源：评论

学校读者我要写书评

暂无评论

Joint estimation for Carrier Frequency Offset and Sampling Frequency Offset in OFDM systems

Joint estimation for Carrier Frequency Offset and Sampling F...

引用

International Conference on Solid-state and Integrated Circuit Technology

作者： Jing Lin Fan Ye Junyan Ren School of Microelectronics Fudan University Shanghai CHINA State-Key Lab of ASIC and System Micro/Nan-Electronics Innovation Platform

ISBN: (纸本)9781479932849

For solving the problem of non-ideal factors introduced from the analog front-end in Orthogonal Frequency Division Multiplexing (OFDM) systems, a joint estimation method of Carrier Frequency Offset (CFO) and Sampling Frequency Offset (SFO) is proposed. This algorithm uses three consecutive preamble symbols to estimate and is robust to large I/Q imbalance. It can reduce interference of Gaussian noise by considering all the samples and taking the advantage of them. Compared to the previous methods, the simulation results show that the proposed method can provide high precision in CFO and SFO estimation, which is robust to large-scale SNR and I/Q imbalance.

关键词： OFDM Estimation Frequency estimation Joints Frequency division multiplexing Frequency conversion Robustness

来源：评论

学校读者我要写书评

暂无评论

Design space exploration for FPGA-based hybrid multicore architecture

Design space exploration for FPGA-based hybrid multicore arc...

引用

IEEE International Conference on Field-Programmable Technology (FPT)

作者： Jian Yan Junqi Yuan Ying Wang Philip Leong Lingli Wang State Key Laboratory of ASIC and System Fudan University Shanghai China School of Electrical and Information Engineering University of Sydney Australia

This paper presents a parameterized system-level design framework, which enables rapid and powerful research for hybrid multicore architecture exploration and hardware/software co-design. The framework comprises the component-based hardware design and application compiler, which make it easy for a designer to build stream-oriented applications with FPGA-based hybrid multicore architectures. The high modularity and parameterization of the framework supports fast multicore architecture exploration of different topologies, routing schemes, processor types, customized hardware processing units and memory system organizations. The compiler tool chain is used to map C/C++ based applications onto the soft processing units. Experimental results targeting the JPEG encoding application demonstrate the feasibility and performance improvement of this framework.

关键词： Multicore processing Hardware Space exploration Transform coding Encoding system-level design

来源：评论

学校读者我要写书评

暂无评论

An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling

引用

Journal of Semiconductors 2013年第3期34卷 76-80页

作者：朱晓石陈迟晓徐佳靓叶凡任俊彦 State Key Laboratory of ASIC & System Fudan University Microelectronics Science and Technology Innovation Platform Fudan University

A sampling switch with an embedded digital-to-skew converter(DSC) is *** proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge sharing structure is used to minimize the *** circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/*** power consumption is 430μW at *** measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs(TI-ADCs) with the proposed DSC switch's *** scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.

关键词： sample-time error digital-to-skew converter bootstrapped switch calibration time-interleaved

来源：评论

学校读者我要写书评

暂无评论

A 131.5GHz, −84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS

A 131.5GHz, −84dBm sensitivity super-regenerative receiver ...

引用

European Conference on Solid-state Circuits (ESSCIRC)

作者： Shunli Ma Hao Yu Yang Shang Wei Meng Lim Junyan Ren State Key Laboratory of ASIC and System Fudan University Shanghai China School of Electrical and Electronic Engineering Nanyang Technological University Singapore

A CMOS high-sensitivity super-regenerative receiver is proposed for millimeter-wave imaging systems. With quench-control signals, two LC-tank oscillators are coupled in-phase by zero-phase-shifter network in a positive feedback loop. This leads to a high oscillatory amplification and improves the detection sensitivity. The circuit is realized in 65nm CMOS with a core area of 0.06 mm 2 . Measurements show that the receiver features a sensitivity of -84dBm, a noise-equivalent-power of 0.615fW/Hz 0.5 , a noise-figure of 7.26 dB and a power consumption of 8.1mW.

关键词： Sensitivity Receivers Oscillators CMOS integrated circuits Imaging CMOS technology Noise measurement

来源：评论

学校读者我要写书评

暂无评论

Equivalent oxide thickness scaling of Al_2O_3/Ge metal-oxide-semiconductor capacitors with ozone post oxidation

引用

Chinese Physics B 2013年第6期22卷 561-564页

作者：孙家宝杨周伟耿阳卢红亮吴汪然叶向东张卫施毅赵毅 School of Electronic Science and Engineering Nanjing University State Key Laboratory of ASIC and System Fudan University State Key Laboratory of Silicon Materials Zhejiang University

Aluminum-oxide films deposited as gate dielectrics on germanium （Ge） by atomic layer deposition were post oxidized in an ozone atmosphere. No additional interfacial layer was electron microscopy and X-ray photoelectron spectroscopy detected by the high-resolution cross-sectional transmission measurements made after the ozone post oxidation （OPO） treatment. Decreases in the equivalent oxide thickness of the OPO-treated Al2O3/Ge MOS capacitors were confirmed. Furthermore, a continuous decrease in the gate leakage current was achieved with increasing OPO treatment time. The results can be attributed to the film quality having been improved by the OPO treatment.

关键词： Al2O3 gate dielectric ozone post oxidation equivalent oxide thickness electrical properties

来源：评论

学校读者我要写书评

暂无评论

Design of Dynamic Digital Circuits with n-Channel Multiple-Input Floating-Gate Transistors

Design of Dynamic Digital Circuits with n-Channel Multiple-I...

引用

IEEE International Symposium on Dependable, Autonomic and Secure Computing (DASC)

作者： Guoqiang Hang Xuanchang Zhou Xiaohui Hu State Key Laboratory of ASIC & System Fudan University Shanghai China School of Information and Electrical Engineering Zhejiang University City College Hangzhou China

Dynamic circuits using n-channel multiple-input floating-gate MOS(FGMOS) transistors to realize binary and ternary logic are presented. In binary domino circuits, the n-channel FGMOS transistors are used to replace the nMOS logic block to simplify the circuit structure. By using the advantage that voltage signals are easy to be added by means of floating gate in multiple-input FGMOS transistor, a summation signal is introduced in binary circuit design. Finally, two dynamic ternary literal circuits are designed using n-channel FGMOS transistors. The proposed voltage-mode dynamic ternary literal circuits have simpler structure. All the proposed dynamic circuits are verified by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology.

关键词： Logic gates Transistors CMOS integrated circuits Couplings Simulation Threshold voltage Inverters

来源：评论

学校读者我要写书评

暂无评论

Variation of Ti Valence with Lithium Content in Lithiated/Delithiated Li_(4)Ti_(5)O_(12) Studied by X-Ray Absorption near the Edge Structure

引用

Chinese Physics Letters 2013年第3期30卷 108-111页

作者： YU Peng-Fei CUI Zhong-Hui MENG Jian-Wei GUO Xiang-Xin State Key Laboratory of High Performance Ceramics and Superfine Microstructure Shanghai Institute of CeramicsChinese Academy of SciencesShanghai 200050 State Key Laboratory of ASIC and System Department of MicroelectronicsFudan UniversityShanghai 200433

Synchrotron-based x-ray absorption near-edge structure(XANES)spectroscopy is applied to investigate the variation of Ti valence in the discharge and charge processes of Li_(4)Ti_(5)O_(12).Through analysis of the XANES data,the average valence of Ti can be calculated,which allows quantitative determination of the ratios of Ti^(3+)/Ti^(4+) as a function of Li content in the *** is found that the ratios in the composites of Li_(4)Ti_(5)O_(12)/acetylene black(AB)-carbon are larger than those in Li_(4)Ti_(5)O_(12)/Ag/AB-carbon after the discharge to 1.1 V,indicating a larger amount of Li inserted into the former than that into the *** finding provides a good explanation for the fact that the Li_(4)Ti_(5)O_(12)/AB-carbon samples exhibit larger storage capacities than the Li_(4)Ti_(5)O_(12)/Ag/AB-carbon ones prepared in this work,concerning the larger Ti^(3+)/Ti^(4+) ratio and the larger amount of Li^(+) inserted in the electrode for satisfying the charge neutralization requirement.

关键词： Li_(4)Ti_(5)O_(12) composites XANES

来源：评论

学校读者我要写书评

暂无评论

Dielectric loss of half-doped manganite La_(0.5)Ca_(0.5)MnO_3

引用

Chinese Physics B 2013年第8期22卷 637-640页

作者：曹先胜吉高峰罗炳成李峰 School of Mathematics and Physics Changzhou University Department of Microelectronics State Key Laboratory of ASIC and Systems Fudan University Shaanxi Key Laboratory of Condensed Matter Structures and Properties School of Science Northwestern Polytechnical University

The dielectric loss tanfi of half-doped manganite ***3 is investigated using Green＇s function technique. The ***3 is described by the Kondo-lattice model in the double exchange limit, taking into account the Jahn- Teller distortion and the super-exchange interaction between the localized electrons. It is found that the intensity of tans decreases with increasing [e]TI, V, and U. It is also observed that the transition temperature Tp rises as l eJTI and U increase. It is worth noting that Tp remains unchanged and the strength of tans increases with increasing g. The calculated dielectric loss results are explained theoretically, and these behaviors are in qualitative agreement with the experimental results.

关键词： multiferroics dielectric loss Lao.sCao.sMnO3

来源：评论

学校读者我要写书评

暂无评论

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with inp...

引用

28th IEEE Symposium on VLSI Circuits, VLSIC 2014

作者： Li, Hao Chen, Shuai Yang, Liqiong Bai, Rui Hu, Weiwu Zhong, Freeman Y. Palermo, Samuel Chiang, Patrick Yin School of Electrical Engineering and Computer Science Oregon State University Corvallis OR 97331 United States Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Texas A and M University College Station TX 77843 United States State Key Laboratory of ASIC and System Fudan University Shanghai 200433 China LSI Corporation San Jose CA 95131 United States

ISBN: (纸本)9781479933273

A quarter-rate forwarded-clock receiver utilizes an edge-rotating 5/4X sub-rate CDR for improved jitter tolerance with low power overhead relative to conventional 2X oversampling CDR systems. Low-voltage operation is achieved with efficient quarter-rate clock generation from an injection-locked oscillator (ILO) and through automatic independent phase rotator control that optimizes timing margin of each input quantizer in the presence of receive-side clock static phase errors and transmitter duty-cycle distortion (DCD). Fabricated in GP 65nm CMOS, the receiver operates up to 16Gb/s with a BER-12, achieves a 1MHz phase tracking bandwidth, tolerates ±50%UIpp DCD on input data, and has 14Gb/s energy efficiency of 560fJ/bit at V DD=0.8V. © 2014 IEEE.

关键词： Clocks

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：