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作者： Gou, Hong-Yan Chen, Sun Ding, Shi-Jin Sun, Qing-Qing Lu, Hong-Liang Zhang, David Wei Wang, Peng-Fei State Key Laboratory of ASIC and System School of Microelectronics Fudan University 220 Handan Road Shanghai 200433 China

The different charge trapping materials HfO2, HfAlO and Al 2O3 have been compared electrically in metal-oxide-semiconductor capacitors with fixed Al2O3 tunneling and blocking layers and Pd-electrode. The capacitance-voltage hysteresis window, memory window, and stress-time dependent flat-band voltage shift increase with increasing the relative content of HfO2 in the charge trapping layer under the same measurement conditions. After programming at + 17 V for 0.1 s and erasing at - 17 V for 0.1 s, successively, the resulting memory window increases from 0.4 V to 3.8 V with increasing the content of HfO2 from 0% (Al2O3) to 100% (HfO2). However, the charge retention of the capacitors gradually worsens in the sequence of Al2O3, HfAlO and HfO2, which accords with the leakage characteristics of the capacitors. Our results reveal that HfAlO (A:H = 1:1) is a more promising charge trapping material than HfO2 and Al2O3 for polysilicon-oxide-nitride- oxide-silicon type memory applications. This is attributed to enough charge storage capacity, high thermal stability and medium dielectric constant. © 2012 Elsevier B.V.

关键词： Atomic layer deposition

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Nitridation of atomic-layer-deposited HfO2/Al2O 3 stacks by NH3 annealing

Nitridation of atomic-layer-deposited HfO2/Al2O 3 stacks by ...

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作者： Liu, Jian-Shuang Geng, Yang Chen, Lin Sun, Qing-Qing Zhou, Peng Lu, Hong-Liang Zhang, David Wei State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai 200433 China

HfO2/Al2O3 stacks are grown on Si (100) substrate by atomic layer deposition and then nitridized using ammonia (NH 3) annealing in the temperature range of 600-900 C. The effects of NH3 annealing temperature on the structural and physical properties are investigated. HfO2 phase changes from monoclinic to orthorhombic with the annealing treatment. Moreover, the increasing of the grain size and decreasing of the valence band maximum with increasing annealing temperature are demonstrated. In addition, the film annealed at 900 C clearly shows that there exists an amorphous Al2O3 layer between partially crystalline HfO2 layer and the Si substrate. © 2012 Elsevier B.V.

关键词： High-k dielectric

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RPSim: A Rapid Prototyping Full-system Simulator for SoC Software Development

RPSim: A Rapid Prototyping Full-System Simulator for SoC Sof...

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International Conference on Networking, Architecture, and Storage (NAS)

作者： Haojun Wang Qinghao Min Yi Li Weihua Zhang Software School Fudan University Shanghai China Shanghai Key Laboratory of Data Science Fudan University Shanghai China State Key Laboratory of ASIC & System Fudan University Shanghai China Parallel Processing Institute Fudan University Shanghai China

Nowadays, the release of SoC products has come to a burst. Time-to-market of these products has been shortened to an extreme, nearly 8 to 12 months. To reduce production period, hardware architects generally combine well-tuned IP cores in their designs. To guarantee the process of SoC software development, which will finally decide the release time of products, a fast prototyping simulation platform for SoC software development should be available as soon as possible after hardware design. However, state-of-the-art SoC simulators lack the support for fast integration of IP core and require time-consuming compiler chain modifications for new instructions. In this paper, we present Prism, an extensible and easy-to-use full-system SoC simulation platform for SoC software development. Two mechanisms are designed and implemented to support fast prototyping for new IP core simulation or new instruction extension without compiler tool chain modifications. First, a hardware and software hybrid mechanism is proposed for IP core fast prototyping. A seamless interface is used to eliminate the differences among IP cores. Second, a configurable library mechanism is designed for new instruction extension. Register dependence can be maintained for detailed timing simulation without compiler tool chain modification. In such a design, the major effort for extension is to specify the elaborate common customization interface. Experimental results show these mechanisms only involve about 0.36% runtime overhead. Based on RPSim, a graduate student only needs write about 40 lines of code and takes less than half an hour to extend a new IP core simulation in RPSim.

关键词： IP networks Frequency modulation Field programmable gate arrays system-on-chip Timing Libraries Software

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A true single-phase clocked full-adder using floating-gate MOS transistor

A true single-phase clocked full-adder using floating-gate M...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Guoqiang Hang Xiaohui Hu Danyan Zhang Yang Yang Jianzhong Wu State Key Laboratory of ASIC & System Fudan University Shanghai CHINA School of Infonnation & Electrical Engineering Zhejiang University City College Hangzhou CHINA School of Computer Science Zhejiang University City College Hangzhou CHINA

ISBN: (纸本)9781479932849

A new true-single-phase clocked (TSPC) full-adder using floating-gate MOS (FGMOS) transistor is presented. In this new design scheme, the logic tree for the sum-generate circuit is realized using only an n-channel multiple-input FGMOS transistor, and the logic for the carry-generate circuit is realized using a complementary FGMOS-based inverter. By using FGMOS transistors, the circuit structure can be dramatically simplified. Since the voltage signals are easy to be added by means of floating gate in FGMOS transistor, a summation signal treated as a medium variable is employed in the circuit design. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology have verified the effectiveness of the proposed circuits. For comparison, the power consumption and the output delay of the proposed TSPC full-adder are measured during the simulations.

关键词： Transistors Abstracts Logic gates Adders

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Biofeedback neuromuscular electrical stimulation front-end for dysphagia treatment

Biofeedback neuromuscular electrical stimulation front-end f...

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IEEE Biomedical Circuits and systems (BIOCAS)

作者： Rongtao Hu Yajie Qin Yinghong Tian Zhiliang Hong Geng Yang Li-rong Zheng Jie Jia Cuiwei Yang Xiaomei Wu Yuanyuan Wang State Key Laboratory of ASIC & System Fudan University Shanghai China Department of Microelectronics East China Normal University Shanghai China ECS School of ICT Stockholm KTH Sweden Department of Rehabilitation Huashan Hospital Shanghai China Department of Electronics Engineering Fudan University Shanghai China

A dedicated front-end for biofeedback neuromuscular electrical stimulation (NESM) system is proposed. For controllable dysphagia treatment, the integrated circuit (IC) provides a stimulator front-end with programmable stimulation parameters (2μA-1mA current amplitude, DC-2KHz frequency, and variable duty cycle) and an electromyogram/impedance (EMG/ETI) readout front-end with programmable gain and bandwidth (42-80dB, 0.1Hz-1.2KHz) for biofeedback. Area-efficient, low-power but high precision current controlling is achieved by inducing the sigma-delta modulator technique in the stimulation channel. The measured impedance and EMG signal are used to determine the stimulation parameters, enabling a closed loop optimized treatment. The proposed front-end is fabricated in a 0.18 μm standard CMOS process technology and dissipates a peak power of 2.3 mW at the supply voltage of 1.8 V. Measurement results on a live person are also provided to validate the system's effectiveness.

关键词： Electromyography Biological control systems Electrical stimulation Current measurement Neuromuscular Electrodes Impedance

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Design of dynamic ternary logic using floating-gate MOS transistor

Design of dynamic ternary logic using floating-gate MOS tran...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Guoqiang Hang Xiaohua Li Xiaohui Hu State Key Laboratory of ASIC & System Fudan University Shanghai China School of Information & Electrical Engineering Zhejiang University City College Hangzhou China Campus Information Center Zhejiang University Hangzhou China

ISBN: (纸本)9781479932849

A new dynamic circuit scheme to realize voltage-mode ternary circuit using floating-gate MOS (FGMOS) transistor is presented. The dynamic ternary inverter and literal circuits with the less complex structure are designed, and they can be implemented by the standard CMOS process with a double-poly layer without any modification of the thresholds. In the proposed scheme, the circuit output is always brought to logic 1 during the pre-charge phase, to avoid charge sharing in cascaded gates, and then the disadvantage of buffering between stages is eliminated. All the proposed circuits are verified by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology.

关键词： Transistors Multivalued logic Abstracts CMOS integrated circuits CMOS technology Logic gates

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A Wirelessly-Powered UWB Sensor Tag with Time-Domain Sensor Interface

A Wirelessly-Powered UWB Sensor Tag with Time-Domain Sensor ...

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IEEE International Symposium on Circuits and systems

作者： Dongxuan Bao Zhuo Zou Qian Wang Majid Baghaei Nejad Li-Rong Zheng State Key Laboratory of ASIC & System Fudan University Shanghai 201203 China iPack Vinn Excellence Center School of Information and Communication Technology KTH-Royal Institute of Technology 164 40 Kista Sweden

ISBN: (纸本)9781479934331

This paper presents a wirelessly-powered sensor tag with a time-domain sensor interface for wireless sensing applications. The tag is remotely powered by RF wave. Instead of traditional approaches employing conventional ADCs for quantization and transmitter for data communication, in this work, a Pulse Position Modulator incorporating simple impulse radio UWB (IR-UWB) transmitter is proposed to convert and transmit the analog sensing information in time domain. The analog signal is compared with an adjustable triangular wave for analog to time conversion in signal-varying environments. Then a UWB transmitter converts the PPM signal to very short pulses and sends it back to the reader. The time interval of UWB pulses represents the original input signal in time domain which can be measured on the reader side by a time-to-digital conversion. This approach not only simplifies the ADC design but also relaxes the number of bits transmitted on the tag side. The sensor tag is designed in 180nm CMOS process. Simulation results demonstrate that the proposed approach reduce transmission power consumption by nearly 3 orders of magnitude over traditional approaches, while consuming only 85 μW for 1.5 MS/s sampling rate.

关键词： time-domain IR-UWB proposed TIME-DOMAIN TAGGING Ultra wideband technologies Sensors input signal Transmitters Analog data communication Short pulses Transmitter Analog

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25th Annual Computational Neuroscience Meeting CNS-2016, Seogwipo City, South Korea, July 2-7, 2016 Abstracts

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BMC NEUROSCIENCE 2016年第1期17卷 1-112页

作者： [Anonymous] Computational Neurobiology Laboratory The Salk Institute for Biological Studies San Diego USA UNIC CNRS Gif sur Yvette France The European Institute for Theoretical Neuroscience (EITN) Paris France ATR Computational Neuroscience Laboratories Kyoto Japan Krembil Research Institute University Health Network Toronto Canada Department of Physiology University of Toronto Toronto Canada Department of Medicine (Neurology) University of Toronto Toronto Canada Department of Physics University of New Hampshire Durham USA Department of Neurophysiology Nencki Institute of Experimental Biology Warsaw Poland Department of Theory Wigner Research Centre for Physics of the Hungarian Academy of Sciences Budapest Hungary Department of Mathematical Sciences KAIST Daejoen Republic of Korea Department of Mathematics University of Houston Houston USA Department of Biochemistry & Cell Biology and Institute of Biosciences and Bioengineering Rice University Houston USA Department of Biology and Biochemistry University of Houston Houston USA Grupo de Neurocomputación Biológica Dpto. de Ingeniería Informática Escuela Politécnica Superior Universidad Autónoma de Madrid Madrid Spain Department of Biological Sciences University of Southern California Los Angeles USA Center for Neuroscience Korea Institute of Science and Technology Seoul South Korea Department of Neurology Albert Einstein College of Medicine Bronx USA Center for Neuroscience KIST Seoul South Korea Department of Neuroscience University of Science and Technology Daejon South Korea Systems Neuroscience Group QIMR Berghofer Medical Research Institute Herston Australia Department of Psychology Yonsei University Seoul South Korea Department of Psychiatry Kyung Hee University Hospital at Gangdong Seoul South Korea Department of Psychiatry Veterans Administration Boston Healthcare System and Harvard Medical School Brockton USA Department of Electrical and Electronic Engineering The University of Melbourne Parkvil

A1 Functional advantages of cell-type heterogeneity in neural circuits Tatyana O. Sharpee A2 Mesoscopic modeling of propagating waves in visual cortex Alain Destexhe A3 Dynamics and biomarkers of mental disorders Mitsuo Kawato F1 Precise recruitment of spiking output at theta frequencies requires dendritic h-channels in multi-compartment models of oriens-lacunosum/moleculare hippocampal interneurons Vladislav Sekulić, Frances K. Skinner F2 Kernel methods in reconstruction of current sources from extracellular potentials for single cells and the whole brains Daniel K. Wójcik, Chaitanya Chintaluri, Dorottya Cserpán, Zoltán Somogyvári F3 The synchronized periods depend on intracellular transcriptional repression mechanisms in circadian clocks. Jae Kyoung Kim, Zachary P. Kilpatrick, Matthew R. Bennett, Kresimir Josić O1 Assessing irregularity and coordination of spiking-bursting rhythms in central pattern generators Irene Elices, David Arroyo, Rafael Levi, Francisco B. Rodriguez, Pablo Varona O2 Regulation of top-down processing by cortically-projecting parvalbumin positive neurons in basal forebrain Eunjin Hwang, Bowon Kim, Hio-Been Han, Tae Kim, James T. McKenna, Ritchie E. Brown, Robert W. McCarley, Jee Hyun Choi O3 Modeling auditory stream segregation, build-up and bistability James Rankin, Pamela Osborn Popp, John Rinzel O4 Strong competition between tonotopic neural ensembles explains pitch-related dynamics of auditory cortex evoked fields Alejandro Tabas, André Rupp, Emili Balaguer-Ballester O5 A simple model of retinal response to multi-electrode stimulation Matias I. Maturana, David B. Grayden, Shaun L. Cloherty, Tatiana Kameneva, Michael R. Ibbotson, Hamish Meffin O6 Noise correlations in V4 area correlate with behavioral performance in visual discrimination task Veronika Koren, Timm Lochmann, Valentin Dragoi, Klaus Obermayer O7 Input-location dependent gain modulation in cerebellar nucleus neurons Maria Psarrou, Maria Schilstra, Neil Davey, Benjamin Torben-Ni

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A 25Gbps, 2x-oversampling CDR using a zero-crossing linearizing phase detector

A 25Gbps, 2x-oversampling CDR using a zero-crossing lineariz...

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IEEE Symposium on Radio Frequency Integrated Circuits (RFIC)

作者： Zhongkai Wang Rui Bai Juncheng Wang Xing Jing Qi Nan Li Sun C. Patrick Yue Zhiliang Hong Patrick Yin Chiang ASIC & System State Key Laboratory Fudan Univ. Shanghai China School of Electrical Engineering and Computer Science Oregon State Univ. Corvallis OR USA Now Qualcomm San Diego CA Hong Univ. of Science and Technology

A 2x-oversampling 25Gbps clock and data recovery (CDR) circuit is proposed that employs a charge-based, zero-crossing linearizing phase detector (ZCL-PD). This technique linearizes the conventional bang-bang CDR system, resulting in low quantization jitter, improved loop bandwidth, and improved input sensitivity. To minimize the power consumption, an injection-locked inverter-based 1:2 divider reduces CML clocking power while maintaining low jitter. The 65nm-CMOS test-chip measurements demonstrate error-free operation for PRBS-7 and PRBS-31, an 120mV differential input sensitivity, a 9MHz jitter transfer bandwidth, 1.08ps/9.63ps (rms/pk-pk) of recovered clock jitter, and 65mW of power consumption.

关键词： Jitter Clocks Quantization (signal) Detectors Bandwidth Charge pumps Sensitivity

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Efficient symbol reliability based decoding for QCNB-LDPC codes

Efficient symbol reliability based decoding for QCNB-LDPC co...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Leixin Zhou Jin Sha Yun Chen Chuan Zhang Zhongfeng Wang School of Electronic Science and Engineering Nanjing University Nanjing China State Key Lab. of ASIC and System Fudan University Shanghai China National Mobile Communications Research Laboratory School of Information Science and Engineering Southeast University Nanjing China Broadcom Corporation Irvine CA USA

ISBN: (纸本)9781479934331

As an extension of binary low-density parity-check (LDPC) codes, non-binary LDPC (NB-LDPC) codes show significantly better performance when the code length is moderate or small. Recently, enhanced iterative hard reliability based (EIHRB) decoding algorithm is proposed to reduce the computation complexity. However, the EIHRB algorithm suffers a lot from significant performance degradation when the column weight is small. In this paper, a symbol reliability based (SRB) decoding algorithm, which also performs well when the column weight is low, is proposed for NB-LDPC decoding to improve the decoding performance. With the same maximum iteration number, around 0.38 dB extra coding gain is achieved. Furthermore, the corresponding efficient decoder architecture is proposed. Comparison results have shown that the proposed SRB algorithm can not only achieve good coding gain, but the cost for hardware implementation is reasonable.

关键词： Decoding Reliability Vectors Iterative decoding Simulation Educational institutions

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