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Effect of charge sharing on the single event transient response of CMOS logic gates

Journal of Semiconductors 2011年第9期32卷 119-124页

作者：段雪岩王丽云来金梅 State Key Laboratory of ASIC & System School of MicroelectronicsFudan University

This paper presents three new types of pulse quenching mechanism（NMOS-to-PMOS,PMOS-to-NMOS and NMOS-to-NMOS） and verifies them using 3-D TCAD mixed mode simulations at the 90 nm node. The three major contributions of this paper are：（1） with the exception of PMOS-to-PMOS,pulse quenching is also prominent for PMOS-to-NMOS and NMOS-to-NMOS in a 90 nm process.（2） Pulse quenching in general correlates weakly with ion LET,but strongly with incident angle and layout style（*** between transistors and n-well contact area）.（3） Compact layout and cascaded inverting stages can be utilized to promote SET pulse quenching in combinatorial circuits.

关键词： single event transient charge sharing pulse quenching 3-D TCAD simulation radiation hardening

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The nano-scale resistive memory effect of graphene oxide

The nano-scale resistive memory effect of graphene oxide

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IEEE Nanotechnology Materials and Devices Conference (NMDC)

作者： H. Q. Wei P. Zhou Q. Q. Sun L. H. Wang Y. Geng D. W. Zhang X. B. Wang ASIC & System State Key Laboratory School of Microelectronics Fudan University Shanghai China School of Materials Science and Engineering Hubei University Wuhan China

ISBN: (纸本)9781467328715

An attractive+ to graphene for a range of applications is graphene oxide (GO). GO is an insulator because of the hydroxyl, carboxyl, carbonyl and epoxide functional groups presenting on the basal surface or edge and becomes a semiconductor or semimetal as it is reduced back toward graphene. Here we demonstrate that graphene oxide can be reversibly reduced and oxidized in nanometer-scale by applying bias voltages by the nano-tip of conductive atomic force microscopy system. The low resistance state (LRS) when reduced and a high resistance state (HRS) when oxidized can be achieved under the opposite applied bias direction. The LRS (around 10 KΩ and HRS (around 40 M Ω) were stable for more than 10 3 s, and no obvious degradation was observed during the tests. Threshold voltages for reduction and oxidation, which can be considered as the set and reset voltages is around -6.5 V and +7 V, respectively. It is shown that the hydrogen (H+) ions and hydroxyl ions (OH-) dissociated from the water meniscus formed between the tip and GO in ambient condition at room temperature plays an essential role in the resistive memory switching. It is also found that the negative bias is responsible for the reduction, which is related the transition from HRS to LRS, and the positive bias is responsible for the oxidation, which is related the transition from LRS to HRS, respectively. Raman spectroscopy and X-ray photoelectron spectroscopy is performed to confirm this resistive memory switching behaviors.

关键词： graphene oxide hydroxyl ion base face Bias voltage semimetals Memory effect FORWARD BIAS negative bias Oxidation graphene Lawrencium insulators Semiconductor materials Oxidized

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Two-dimensional simulation of Mid-infrared quantum cascade lasers: Temperature and field dependent analysis

Two-dimensional simulation of Mid-infrared quantum cascade l...

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12th International Conference on Numerical Simulation of Optoelectronic Devices, NUSOD 2012

作者： Li, Ying-Ying Simon Li, Z.-M. Ru, Guo-Ping State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai 200433 China Crosslight Software Inc. 121-3989 Henning Dr. Burnaby BC V5C 6P8 Canada

ISBN: (纸本)9781467316040

We report on a 2D simulation study of a couple of mid-infrared quantum cascade lasers based on the integration of a number of optoelectronic models. Quantum mechanical computation was performed to find the quantization states and a rate equation approach was used to compute the optical gain. Temperature and field dependence effects are taken into account in optical gain model to make a realistic simulation of QCLs. The simulation study compared the integrated models with experimental data with different structures and at different temperatures. Reasonable agreements between experiment and simulation have been obtained. © 2012 IEEE.

关键词： Quantum cascade lasers

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Investigation of single-transistor active pixel image sensor compatible with dual-poly-gate technology

Investigation of single-transistor active pixel image sensor...

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Symposium on Photonics and Optoelectronics

作者： Xin-Yan Liu Xi Lin Cheng-Wei Cao Qing-Qing Sun Paul-Chang Lin Yi-Jun Bian Cheng Xing Peng-Fei Wang David Wei Zhang State Key Laboratory of ASIC and System Dept. of Microelectronics Fudan University Semiconductor Manufacturing International Corp. (SMIC)

ISBN: (纸本)9781457709098

A single-transistor active pixel image sensor compatible with dual-poly-gate technology is investigated in this paper. The integration compatibility is studied by integrating this device using EEPROM fabrication processes. The operation mechanism, light sensing performance, and non-destructive reading of this image sensor will be discussed.

关键词： APS Image sensor Dual gate-poly Fill factor

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Trapezoid mesa trench metal-oxide semiconductor barrier Schottky rectifier:an improved Schottky rectifier with better reverse characteristics

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Chinese Physics B 2011年第8期20卷 376-383页

作者：李惟一茹国平蒋玉龙阮刚 State Key Laboratory of ASIC and System Department of MicroelectronicsFudan University

An improved structure of Schottky rectifier, called a trapezoid mesa trench metal oxide semiconductor （MOS） barrier Schottky rectifier （TM-TMBS）, is proposed and studied by two-dimensional numerical simulations. Both forward and especially better reverse I-V characteristics, including lower leakage current and higher breakdown voltage, are demonstrated by comparing our proposed TM-TMBS with a regular trench MOS barrier Schottky rectifier （TMBS） as well as a conventional planar Schottky barrier diode rectifier. Optimized device parameters corresponding to the requirement for high breakdown voltage are given. With optimized parameters, TM-TMBS attains a breakdown voltage of 186 V, which is 6.3% larger than that of the optimized TMBS, and a leakage current of 4.3×10^-6 A/cm2, which is 26% smaller than that of the optimized TMBS. The relationship between optimized breakdown voltage and some device parameters is studied. Explanations and design rules are given according to this relationship.

关键词： Schottky rectifier pinch-off effect breakdown power device

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Erratum:An approach for determining equivalent circuit model of on-chip inductors

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Microwave and Optical Technology Letters 2013年第1期56卷

作者： Na Yan Chen Yang Jianjun Gao ASIC & System State Key Laboratory Fudan University Shanghai 201203 China Shanghai Institute of Microsystem and Information Technology State Key Laboratory of Transducer Technology Shanghai China School of Information Science and Technology East China Normal University Shanghai 200062 People's Republic of China

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Peripheral Ferroelectric Domain Switching and Polarization Fatigue in Nonvolatile Memory Elements of Continuous Pt/SrBi_(2)Ta_(2)O_(9)/Pt Thin-Film Capacitors

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Chinese Physics Letters 2011年第7期28卷 275-277页

作者： CHEN Min-Chuan JIANG An-Quan State Key Laboratory of ASIC&System Department of MicroelectronicsFudan UniversityShanghai 200433

We verify the domain sideway motion around the peripheral regions of the crossed capacitors of top and bottom electrode bars without electrode *** avoid the crosstalk problem between adjacent memory cells,the safe distance between adjacent elements of Pt/SrBi_(2)Ta_(2)O_(9)/Pt thin−film capacitors is estimated to be 0.156µ***,the fatigue of Pt/SrBi_(2)Ta_(2)O_(9)/Pt thin-film capacitors is independent of the individual memory size due to the absence of etching damage.

关键词： electrode volatile film

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Investigation of Schottky junction and MOS technology for III–V compound semiconductor MOSFET application

Investigation of Schottky junction and MOS technology for II...

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International Workshop on Junction Technology

作者： Jun Chen Teng-Chieh Ku Ming-Fu Li Albert Chin State Key Laboratory ASIC and System Department of Microelectronics Fudan University Shanghai China Department of Electronics Engineering and Institute of Electronics National Chiao Tung University Hsinchu Taiwan

This paper explores two low temperature technological developments related to future n-MOSFETs using III-V semiconductors as channel materials. (1). It was found that Yb-GaAs Schottky contact with RTA at 500°C for 30s has good rectifying characteristics, low effective electron barrier height, low sheet resistivity, atomically sharp junction with GaAs. These properties are suitable for source/drain (S/D) formation in GaAs n-MOSFETs. (2). GaAs MOS capacitors were fabricated by E-gun deposition of LaAlO 3 (LAO) dielectric and PVD deposition of TaN electrode. The capacitors with well-behaved CV characteristics with EOT=3nm, gate leakage currents 7.5×10 -3 A/cm 2 for 500°C RTA treated samples at V fb -1V were achieved.

关键词： Capacitors MOSFET circuits Gallium arsenide Silicon Annealing Fitting Abstracts

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A 10-bit 80-MS/s opamp-sharing pipelined ADC with a switch-embedded dual-input MDAC

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Journal of Semiconductors 2011年第2期32卷 102-107页

作者：尹睿廖友春张卫唐长文 ASIC & System State Key Laboratory Fudan University China Ratio Microelectronics Co. Ltd Ratio Microelectronics Co.Ltd

A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB （ENOB = 9.69 bits） and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.

关键词： pipelined ADC opamp-sharing low power switch-embedded dual-input MDAC

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Influence of under-bump metallurgy and solder alloys on the crack in the wafer level chip scale packaging

Influence of under-bump metallurgy and solder alloys on the ...

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IEEE Conference on Electron Devices and Solid-state Circuits

作者： J.H. Lu M. Xu H. Zhang H.L. Lu D.W. Zhang Shanghai Ultra-precision Optical Manufacturing Engineering Center Department of Optical Science and Engineering Fudan University Shanghai China State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai China

The finite element method (FEM) is employed to investigate the solder crack mechanism in wafer level chip scale packaging (WLCSP). The location of the initial crack is calculated and is compared to the experimental one. Moreover, the impact of the following three aspects, e.g. under-bump metallurgy (UBM) materials, solder alloy, and the thickness of the UBM layers on the initial crack growth in solder is investigated by calculating J-integral, respectively, which reflects the possibility of crack growth. It is concluded that the J-integral values in 96.5Sn3.5Ag solder and the Au-Ni-Cu-Ti UBM material are smaller than other cases.

关键词： Finite element analysis Materials Stress Nickel Gold Strain

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