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Journal of Semiconductors 2024年第10期45卷 7-19页

作者： Jie Ma Shenglong Zhuo Lei Qiu Yuzhu Gao Yifan Wu Ming Zhong Rui Bai Miao Sun Patrick Yin Chiang The College of Electronics and Information Engineering Tongji UniversityShanghai 200092China State Key Laboratory of ASIC&System Fudan UniversityShanghai 201203China School of Electrical and Electronic Engineering Nanyang Technological UniversitySingapore Lyne Technologies Shanghai 201203China

In recent years,propelled by the rapid iterative advancements in digital imaging technology and the semiconductor industry,encompassing microelectronic design,manufacturing,packaging,and testing,time-of-flight(ToF)-based imaging systems for acquiring depth information have garnered considerable attention from both academia and *** technology has emerged as a focal point of research within the realm of 3D *** to its relatively straightforward principles and exceptional performance,ToF technology finds extensive applications across various domains including human−computer interaction,autonomous driving,industrial inspection,medical and healthcare,augmented reality,smart homes,and 3D reconstruction,among ***,the increasing maturity of ToF-based LiDAR systems is evident in current *** paper comprehensively reviews the fundamental principles of ToF technology and LiDAR systems,alongside recent research *** elucidates the innovative aspects and technical challenges encountered in both transmitter(TX)and receiver(RX),providing detailed discussions on corresponding ***,the paper explores prospective avenues for future research,offering valuable insights for subsequent investigations.

关键词： time of flight light detection and ranging transmitter receiver

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Terahertz transmitter demonstration of the simultaneous transmission of optical and electrical terahertz band signals at 1 Tb/s bit rate and 50 m wireless delivery

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Science China(Technological Sciences) 2025年第3期68卷 380-382页

作者： Kaihui WANG Jianjun YU Chengzhen BIAN Junjie DING Jiao ZHANG Min ZHU Xiongwei YANG Weiping LI Yi WEI Mingxu WANG Qiutong ZHANG Ying WU Bo LIU Wen ZHOU Yuancheng CAI Bingchang HUA Mingzheng LEI Yucong ZOU Jianguo YU Feng ZHAO State Key Laboratory of ASIC and System Fudan UniversityShanghai200433China Purple Mountain Laboratories Nanjing211111China School of Electronic Engineering Beijing University of Posts and TelecommunicationsBeijing100876China School of Electronic Engineering Xi’an University of Posts and TelecommunicationsXi’an710121China

In recent years,free space optical communication(FSO)has been a hot topic in satellite-to-ground communications,inter-satellite communications,and wireless access networks[1-4].It has the advantages of rich spectrum resources,no need for spectrum authorization,high spectrum efficiency verified by experiments,narrow beam angle,and low space loss under good *** point-to-point communications,the beam angle makes the FSO almost immune to multipath effects,and low-complexity Digital Signal Processing(DSP)algorithms can be used for recovery demodulation.

关键词： optical multipath spectrum

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A CFET Unit Cell based MUX21 design strategy 16

A CFET Unit Cell based MUX21 design strategy

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Zhu, Xiao-Na Wei, Chen-Cheng Ding, Rong-Zheng Yu, Shao-Feng Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai200433 China Jiashan Fudan Institute China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

With the Moore's law approaching ultimate limitation, device structure has been revolutionary changing, from FinFET to GAA FET, and then a new semiconductor device structure, CFET, has been regarded the continuing structure after GAA. CFET has significant area miniaturization advantages, but its folding N/PFET vertically brings new difficulties in process flow and new strategies for design enablement like in standard cell library. In this paper, we proposed the design consideration priority in CFET unit cell constructed standard cell library, and give examples like MUX21in obeying our rule. Two different schematics of MUX21 are designed at multiple levels: process flow, layout, and circuit performance. The proposed rule in CFET unit cell for standard library cell and the specific DTCO flow in this MUX21 circuit can provide the pathway for other circuit designs of standard cell library composed of CFET unit cell. © 2022 IEEE.

关键词： Cytology

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A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter 44

A Self Bias-flip Piezoelectric Energy Harvester Array withou...

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44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023

作者： Li, Zhen Chen, Zhiyuan Law, Man-Kay Du, Sijun Cheng, Xu Zeng, Xiaoyang Han, Jun Fudan University State Key Laboratory of Asic and System Shanghai China University of Macau State Key Laboratory of Analog and Mixed-Signal Vlsi China Delft University of Technology Department of Microelectronics Delft Netherlands

ISBN: (纸本)9798350399486

With the advent of the lnternet-of-Things (1oT) era, sensor nodes are required in almost all fields to achieve a better interaction between humans and the environment. Piezoelectric energy harvester (PEH), which exhibits an equivalent electrical model of an AC current source /P in parallel with the inherent capacitor CP, is a promising technology to resolve the energy problem of such sensor nodes. Recently, inductor-based rectifiers, capacitor-based rectifiers and hybrid rectifiers have been proposed to improve the energy extraction efficiency of PEH devices [1]-[5]. However, these structures all require the aid of additional capacitors or inductors to achieve bias-flip operation, as illustrated in Fig. 1. These extra passive devices are typically large, which can be a major bottleneck in system-volumeconstrained applications such as MEMS [4]. In response to the above problem, this work proposes a novel 8-phase self bias-flip PEH interface with charge recycling and reusing (SBFRR). By using the C P of 4 PEHs as flipping capacitors, this scheme achieves a high voltage flipping efficiency without using extra energy reservoirs. The 4 C P can also serve as flying capacitors to achieve switched-PEH DC-DC (SPDC) conversion for MPPT, while maintaining a MOPIR of >3.5× with a PEH input voltage (Vp) from 0. 78Vto4.9V. © 2023 IEEE.

关键词： Sensor nodes

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Critical band-to-band-tunnelling based optoelectronic memory

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Light(Science & Applications) 2025年第3期14卷 757-766页

作者： Hangyu xu Runzhang Xie Jinshui Miao Zhenhan Zhang Haonan Ge Xumina Shi Min Luo Jinjin Wang Tangxin Li Xiao Fu Johnny CHo Peng Zhou Fang Wang Weida Hu State Key Laboratory of Infrared Physics Shanghai Institute of Technical PhysicsChinese Academy of Sciences500 Yu Tian Road200083ShanghaiChina University of Chinese Academy of Sciences BeijingChina ASIC&System State Key Laboratory School of MicroelectronicsFudan UniversityShanghaiChina Shanghai Research Institute for Intelligent Autonomous Systems Tongji University200092ShanghaiChina Department of Materials Science and Engineering and State Key Laboratory of Terahertz and Millimeter Waves City University of Hong KongKowloon TongHong Kong SARChina

Neuromorphic vision hardware,embedded with multiple functions,has recently emerged as a potent platform for machine *** realize memory in sensor functions,reconfigurable and non-volatile manipulation of photocarriers is highly ***,previous technologies bear mechanism challenges,such as the ambiguous optoelectronic memory mechanism and high potential barrier,resulting in a limited response speed and a high operating ***,for the first time,we propose a critical band-to-band tunnelling(BTBT)based device that combines sensing,integration and memory *** nearly infinitesimal barrier facilitates the tunnelling process,resulting in a broadband application range(94o nm).Furthermore,the observation of dual negative differential resistance(NDR)points confirms that the critical BTBT of photocarriers contributes to the sub-microsecond photomemory *** the photomemory speed,with no motion blur,is important for motion detection,the critical BTBT memory is expected to enable moving target tracking and recognition,underscoring its superiority in intelligentperception.

关键词： photocarrier manipulation optoelectronic memory mechanism machine visionto photomemory speed optoelectronic memory critical band band tunnelling neuromorphic vision hardware negative differential resistance

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A 12.87-dB Gain 10.5-dBm OPldB60-to-66-GHz LNA in 0.15-μm GaAs pHEMT Technology

A 12.87-dB Gain 10.5-dBm OPldB60-to-66-GHz LNA in 0.15-μm G...

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2022 IEEE the Asia Pacific Conference on Postgraduate Research in microelectronics and Electronics, PrimeAsia 2022

作者： Li, Xuefeng Wang, Yuting Wu, Tianxiang Chen, Yong Ren, Junyan Ma, Shunli School of Microelectronics Fudan University State Key Laboratory of ASIC and System Shanghai China State Key Laboratory of ASIC and System School of Information Science and Technology Fudan University Shanghai China University of Macau State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST Macao China

ISBN: (纸本)9781665450690

This paper presents a V-band low noise amplifier (LNA) implemented in a 0.15-μm Gallium Arsenide (GaAs) pseudomorphic high electron-mobility transistor (pHEMT) technology. The LNA adopts a three-stage common-source (CS) topology. Each transistor has a bias circuit, and the microstrip-line inductor is used to realize the input noise matching network, the interstage, and the output matching network. Circuit simulations show that our LNA scores a 12.87-dB small-signal gain, the 3-dB bandwidth ranges from 60 GHz to 66 GHz, and the current consumption is 30 mA under a 5-V supply voltage. Its noise figure is 5.9 dB, and the output 1-dB compression point is 10.5 dBm. The chip area is 1.32× 1.5mm2. © 2022 IEEE.

关键词： Low noise amplifiers

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A Reusable AI acceleration Architecture based on Matrix Multiplication for Convolutional Neural Network with Digital Signal ProcessingTasks 15

A Reusable AI acceleration Architecture based on Matrix Mult...

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15th IEEE International Conference on asic, asicON 2023

作者： Chen, Bisheng Li, Xiayu Lu, Jicheng Yu, Jun Fudan University State Key Laboratory of ASIC and System Shanghai200433 China Shanghai Fudan Microelectronics Group Co. Ltd Shanghai200000 China

ISBN: (纸本)9798350312980

As AI begins to face more complex application scenarios, such as intelligent radar, autopilot and intelligent 5G, it often needs to work together with other traditional algorithms, mainly Digital Signal Processing (DSP) algorithms now. The proposed heterogeneous architecture with an AI core (on asic, for CNN) and IP core (on FPGA, for DSP) is usually adopted, but that's inefficient due to the inconsistency in data transmission and operating frequency between chips. In order to solve this problem, this paper has proposed a reusable architecture based on Matrix Multiplication, which supports convolution, FFT and FIR operations on asic. We first analyzed the relationship among Convolution, FFT and FIR and find the best reusable architecture is Matrix multiplication. Then we decomposed the Convolution, FFT and FIR into Matrix multiplication, and designed the hardware architecture for them. Finally, we used Image registration algorithm to test the performance of our architecture, and get 500% speed up. © 2023 IEEE.

关键词： AI Acceleration Fast Fourier Transform (FFT) Finite Impulse Response (FIR) Reusable Architecture

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A 250MS/s, 12 Bit Pipeline-SAR ADC Using Coarse-Fine Ring Amplifier

A 250MS/s, 12 Bit Pipeline-SAR ADC Using Coarse-Fine Ring Am...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Linghao Liu Junyan Ren Fan Ye Department of Microelectronics State Key Laboratory of ASIC and System Fudan University Shanghai China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

The ring amplifier is an energy effective choice for high performance pipeline ADC. However, sensitivity to process, supply voltage and temperature (PVT) variations and complex stability mechanism make it less practical. This brief introduces a coarse-fine ring amplifier (CFRingAmp) that allows individual designs of large-signal and small-signal processes. With a large and a smaller dead-zones switched by the self-detect-and-switch block, both stability and accuracy are well designed over corners. Furthermore, a 250MS/s, 12-bit pipeline-SAR ADC is implemented adopting the proposed CFRingAmp. Simulated in 28nm CMOS, the ADC achieves an SNDR of 64.1 dB and an SFDR of 74.9 dB over corners at Nyquist frequency while consuming 4.5mW, resulting a Walden figure-of merit (FoM) of 12.7 fJ/conversion step.

关键词： Temperature sensors Accuracy Sensitivity Simulation Voltage Switches Stability analysis Circuit stability Registers Thermal stability

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Sub-SA: Strengthen In-Context Learning via Submodular Selective Annotation 27

Sub-SA: Strengthen In-Context Learning via Submodular Select...

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27th European Conference on Artificial Intelligence, ECAI 2024

作者： Qian, Jian Sun, Miao Zhou, Sifan Zhao, Ziyu Hun, Ruizhi Chiang, Patrick State Key Laboratory of ASIC and System Fudan University Shanghai China School of Electrical and Electronic Engineering Nanyang Technological University Singapore School of Automation Southeast University Nanjing China

ISBN: (纸本)9781643685489

In-context learning (ICL) leverages in-context examples as prompts for the predictions of Large Language Models (LLMs). These prompts play a crucial role in achieving strong performance. However, the selection of suitable prompts from a large pool of labeled examples often entails significant annotation costs. To address this challenge, we propose Sub-SA (Submodular Selective Annotation), a submodule-based selective annotation method. The aim of Sub-SA is to reduce annotation costs while improving the quality of in-context examples and minimizing the time consumption of the selection process. In Sub-SA, we design a submodular function that facilitates effective subset selection for annotation and demonstrates the characteristics of monotonically and submodularity from the theoretical perspective. Specifically, we propose RPR (Reward and Penalty Regularization) to better balance the diversity and representativeness of the unlabeled dataset attributed to a reward term and a penalty term, respectively. Consequently, the selection for annotations can be effectively addressed with a simple yet effective greedy search algorithm based on the submodular function. Finally, we apply the similarity prompt retrieval to get the examples for ICL. Compared to existing selective annotation approaches, Sub-SA offers two main advantages. (1.) Sub-SA operates in an end-to-end, unsupervised manner, and significantly reduces the time consumption of the selection process (from hours-level to millisecond-level). (2.) Sub-SA enables a better balance between data diversity and representativeness and obtains state-of-the-art performance. Meanwhile, the theoretical support guarantees their reliability and scalability in practical scenarios. Extensive experiments conducted on diverse models and datasets demonstrate the superiority of Sub-SA over previous methods, achieving millisecond(ms)-level time selection and remarkable performance gains. The efficiency and effectiveness of Sub-SA make it

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Implementation of Multi-Channel TEC Temperature Control system 2

Implementation of Multi-Channel TEC Temperature Control Syst...

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2nd International Conference on Computer Science, Electronic Information Engineering and Intelligent Control Technology, CEI 2022

作者： Jiang, Menxue Han, Shuo Ding, Chenyang Academy for Engineering and Technology Fudan University Shanghai China School of Microelectronics Fudan University State Key Laboratory of Asic and System Shanghai China

ISBN: (数字)9781665476164

ISBN: (纸本)9781665476164

This paper develops a thermoelectric cooler (TEC) temperature control system based on the field-programmable gate array (FPGA). Multi-channel analog-to-digital converters (ADCs) acquire temperature data from the temperature sensors, with resolution of 0.002°C. The noises of the acquired data are processed and reduced using the principle of noise correlation, which is realized in an integrated Digital Signal Processing (DSP). Temperature control algorithm is implemented in the FPGA. Control signals are sent to multi-channel digital to analog converters (DACs) to control the current amplifiers, which drive multiple thermal actuators to heat or cool a temperature-sensitive plant. An ARM microcontroller is used to exchange data between DSP and FPGA. Such a system can be used for temperature control of a micro-positioner. © 2022 IEEE.

关键词： Digital to analog conversion

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