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检索条件"机构=School of Microelectronics and State Key Laboratory of ASIC and System"

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Modulation of Schottky barrier height for NiSi/Si(110) diodes using an antimony interlayer

Modulation of Schottky barrier height for NiSi/Si(110) diode...

引用

IEEE International Conference on Interconnect Technology

作者： Xiao Guo Yao-Juan Xu Yu-Long Jiang Guo-Ping Ru Bing-Zong Li Asic and System State Key Laboratory Department of Microelectronics Fudan University Shanghai China

The barrier height modulation of Ni-silicided Schottky contacts fabricated on n-Si(100), n-Si(110), p-Si(100) and p-Si(110) substrate using an antimony (Sb) interlayer was investigated. The Sb layer was directly sputter-deposited on Si substrate followed by the regular Ni deposition and rapid thermal annealing. It is revealed that NiSi can still form even with the Sb interlayer and the effective Schottky barrier height can be significantly modulated on all kinds of Si substrates.

关键词： Substrates Nickel Silicon Annealing Schottky barriers Schottky diodes Modulation

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Flexible and efficient FEC decoders supporting multiple transmission standards

Flexible and efficient FEC decoders supporting multiple tran...

引用

International SoC Design Conference, ISOCC

作者： Yun Chen Changsheng Zhou Yuebin Huang Shuangqu Huang Xiaoyang Zeng Department of Microelectronics State Key Laboratory of ASIC and System Fudan University Shanghai China

An important trend of the modern mobile device is that a single user terminal that will be capable of receiving signals of multiple different transmission standards. Most of these transmission standards employ a forward error correction decoding, including Reed-Solomon, Viterbi, Turbo and low-density parity check and so on. In this overview paper we review several programmable and area-efficient decoder architectures within one hardware platform. We show, in the case of guaranteed throughput performance, compared with multi-core implementation way, better power consumption performance can be gotten.

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A Simulation Study of Vertical Tunnel Field Effect Transistors

A Simulation Study of Vertical Tunnel Field Effect Transisto...

引用

2011 IEEE 9th International Conference on asic(2011年第九届IEEE国际专用集成电路大会)

作者： Zhong-Fang Han Guo-Ping Ru Gang Ruan State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai 200433 China

We report a simulation study of the characteristics of a new tunnel field effect transistor (TFET), i.e., vertical TFET (VTFET). The new VTFET has a different working principle compared with the traditional lateral TFET (LTFET), which most of the recent studies are focused on. Although both type TFETs are based on band to band tunneling, the tunneling occurs perpendicular to the oxide-Si interface in the VTFET whereas it occurs parallel in LTFET. The VTFET has many advantages compared with the LTFET, such as a steeper subthreshold slope as the gate voltage control the tunneling directly. The steep subthreshold slope results in low OFF current and capability for low power operation.

关键词： Logic gates MOSFET circuits Immune system

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Effect of Structural Parameters on the Performance and Variations of Nanosizes PNIN Tunneling Field Effect Transistor

Effect of Structural Parameters on the Performance and Varia...

引用

2011 IEEE 9th International Conference on asic(2011年第九届IEEE国际专用集成电路大会)

作者： S. Q. Cheng C. J. Yao D. M. Huang State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai 200433 China

The characteristics of PNIN tunneling field effect transistor (TFET) with nanometer sizes are investigated using TCAD simulation. The results show that the performance and variations of the' device strongly depends on the key parameters such as the thickness and the doping of the middle N layer. (1) An increase in the thickness of the N layer to ~5 run will effectively enhance the drive current, reduce the electric field normal to the Si/SiO2 interface (Ex), and reduce the variation of the threshold voltage induced by the variation in the N layer thickness. (2) A decrease in the thickness of Si film down to ~5 run will also reduce Ex, but with minor effect on the on current. Therefore, the overall characteristic of PNIN devices improves with reducing the Tsi. (3) A proper doping such as ~2xl0l9cm-3 in the N layer can remove the dependence and therefore the variation of the threshold voltage on the thickness of Si film.

关键词： Silicon Germanium Films Semiconductor process modeling Very large scale integration Logic gates Neodymium

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A method to build reconfigurable architectures by extracting common subgraphs

A method to build reconfigurable architectures by extracting...

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2011 IEEE 9th International Conference on asic, asicON 2011

作者： Zhang, Tianyun Zhang, Rui Wang, Lingli Hu, Yu Software School Fudan University Shanghai 200433 China State Key Laboratory of ASIC and System Fudan University Shanghai 200433 China Electrical and Computer Engineering Department University of Alberta Canada

ISBN: (纸本)9781612841908

In this paper, we present a novel method to build reconfigurable architectures. Because an RTL description of a circuit can be converted to a data flow graph (DFG), our method is based on graph mining which aims to extract the common subgraphs among different benchmarks. A tool flow is proposed to convert benchmarks to data flow graphs and extract the common subgraphs. Benchmarks in the field of Error Checking and Correcting (ECC) are selected in the experiment to demonstrate that our method is correct and practical. © 2011 IEEE.

关键词： Data flow graphs

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Electrochemical Biosensor Based on Modified Graphene Oxide for Tuberculosis Diagnosis

Electrochemical Biosensor Based on Modified Graphene Oxide f...

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2011 IEEE 9th International Conference on asic(2011年第九届IEEE国际专用集成电路大会)

作者： Pei Zhang Xiaosen Chai Chun Xu Jia Zhou State Key Laboratory of ASIC & System Department of Microelectronics Fudan University. Shanghai 200433 China

In this paper, graphene oxide (GO) was modified insitu on an electrochemical electrode array for attachment of protein. GO suspension made from natural graphite flakes was directly dip-coated onto the Au working electrodes. Detected by cyclic voltammetry, the peak current of GO on Au electrode increased by 1μA as compared with bare gold electrode. Modified graphgene oxide (MGO) with stable active esters was formed by in-situ modifying GO with N-ethyl-N'-(3-dimethylaminopropyI) carbodiimide hydrochloride (EDAC)/ N-hydroxysuccinimide (NHS). MGO was ready for protein attachment. An immunesensor chip (GO-antigen) was prepared by tuberculosis (TB) antigens bound with MGO. The peak of CV curve of GO-antigen increased by about 3μA as compared with that of MGO, however, after the GO-antigen reaction with the antibody, the peak of the current decreased 4μA. Such results showed potential applications of the immunosensor.

关键词： Graphene oxide Biosensor Electrochemistry Immunosensor

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Pattern transfer of nano-scale ferroelectric PZT gratings by a reversal nanoimprint lithography

Pattern transfer of nano-scale ferroelectric PZT gratings by...

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作者： Li, Zhi-Dong Shen, Zhen-Kui Hui, Wen-Yuan Qiu, Zhi-Jun Qu, Xin-Ping Chen, Yi-Fang Liu, Ran State Key Lab of Asic and System Department of Microelectronics Fudan University Shanghai 200433 China Rutherford Appleton Laboratory STFC Chilton Didcot Oxon OX11 0QX United Kingdom Micro and Nanotechnology Centre United Kingdom School of Microelectronics Fudan University 220 Handan Road Shanghai China

Nanoscale PZT gratings are successfully transferred to a Pt substrate using reversal nanoimprint technique without any chemical etch processes. The transfer process is preliminarily studied by measuring the surface topography of PZT coated on templates before transferring as well as the transferred patterns on substrates. Piezoelectric force microscopy (PFM) and Raman spectroscopy are used to investigate the transferred PZT nanostructures after annealing. Good ferroelectric and structural properties have been demonstrated by the transferred PZT nanostructures, indicating that this reversal imprint technique is applicable for forming nanoscale PZT domains, which may lead to the manufactures of high density data storage devices at economic cost. © 2011 Elsevier B.V. All rights reserved.

关键词： Nanoimprint lithography

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Silicon nanowires by combined nanoimprint and angle deposition for gas sensing applications

Silicon nanowires by combined nanoimprint and angle depositi...

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作者： Gao, Chen Xu, Zhen-Cheng Deng, Shao-Ren Wan, Jing Chen, Yifang Liu, Ran Huq, Ejaz Qu, Xin-Ping State Key Lab of ASIC and System Department of Microelectronics Fudan University Shanghai 200433 China Rutherford Appleton Laboratory Chilton Didcot Oxon OX11 0QX United Kingdom Nanoscience and Nanotechnology Micro and Nanotechnology Centre United Kingdom School of Microelectronics Fudan University 220 Handan Road Shanghai China

In this work, we demonstrate the fabrication of silicon nanowires, with their widths ranging from 22 nm to 110 nm, using the combination of bilayer nanoimprint and angle deposition. The approach makes the widths of the nanowires adjustable, offering an alternative solution for high-resolution, low-cost, and high-throughput fabrication of nanowire sensors. Using this approach, silicon nanowires with different widths are formed on the boron-doped top Si layers of the SOI substrates, and are used as sensing parts of the gas sensors. The Si nanowire sensors with wire widths of 60 nm and 90 nm demonstrate relative sensitivities of 155% and 44% to the testing gas of NO2. © 2011 Elsevier B.V. All rights reserved.

关键词： Nanowires

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A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter

A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on ape...

引用

7th IEEE Asian Solid-state Circuits Conference, A-SSCC 2011

作者： Cai, Deyun Fu, Haipeng Ren, Junyan Li, Wei Li, Ning Yu, Hao Yeo, Kiat Seng State Key Laboratory of ASIC and System Fudan University Shanghai 201203 China Micro-/Nano Science and Innovation Platform Fudan University Shanghai 201203 China Virtus Laboratory School of EEE Nanyang Technological University Singapore Singapore

ISBN: (纸本)9781467303989

This paper presents a 2.1-GHz PLL with low power consumption, low in-band phase noise and low reference spur. A new aperture-phase detector (APD) compares the phases between reference and VCO output in a time window, which eliminates the power and noise contributions from the divider. At the end of phase detection, a phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error and then controls the current amplitude of the following charge pump (CP) circuit. When transferred to PLL output, CP noise is not multiplied by N2 compared with a conventional PLL, which leads to the PLL with lower in-band phase noise. In the proposed CP, the charging and discharging currents have equal pulse width and equal amplitude close to zero when PLL is locked, resulting in a low reference spur and super-low power consumption of CP. The proposed PLL is implemented in TSMC 0.13μm CMOS process, which consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm x 0.86 mm excluding PAD. Measurement results indicate that the PLL achieves a reference spur level of -80dBc/-74dBc, and an in-band phase noise of -103 dBc/Hz at 100 kHz offset. © 2011 IEEE.

关键词： Phase locked loops

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A practical method for multi-domain clock skew optimization 11

A practical method for multi-domain clock skew optimization

引用

Asia and South Pacific Design Automation Conference

作者： Yanling Zhi Hai Zhou Xuan Zeng State Key Laboratory of ASIC & System Microelectronics Department Fudan University China Department of EECS Northwestern University USA

ISBN: (纸本)9781424475162

Clock skew scheduling is an effective technique in performance optimization of sequential circuits. However, with process variations, it becomes more difficult to reliably implement a wide spectrum of clock delays at the registers. Multidomain clock skew scheduling is a good option to overcome this limitation. In this paper, we propose a practical method to efficiently and optimally solve this problem. A framework based on branch-and-bound is carefully designed to search for the optimal clocking domain assignment, and a greedy clustering algorithm is developed to quickly estimate the upper bound of cycle period for a given branch. Experiment results on ISCAS89 sequential benchmarks show both the optimality and efficiency of our method compared with previous works.

关键词： Registers Clocks Clustering algorithms Upper bound Timing Optimization Merging

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