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IEEE International Nanoelectronics Conference (INEC)

作者： Gongli Xiao Xiang Yao Xinming Ji Jia Zhou Zongming Bao Yiping Huang State Key Laboratory of ASIC & System Department of Microelectronics Fudan University Shanghai China Information & Communications College Guilin University of Electronic and Technology Guilin China

The enhanced middle-infrared light transmission through Au/SiO x N y /Au aperture arrays by changing the refractive index and the thickness of a dielectric layer was studied experimentally. The results indicated that the transmission spectrum was highly dependent on the refractive index and the thickness of SiO x N y . We found that the transmission peaks redshifted regularly along with the refractive index from 1.6 to 1.8, owing to the role of surface plasmon polaritons (SPP) coupling in the Au/SiO x N y /Au cascaded structure. Simultaneously, a higher transmission efficiency and narrower transmission peak was obtained in Au/SiO 2.1 N 0.3 /Au cascaded structure with small refractive index (1.6) than in Au/ SiO 0.6 N1/Au cascaded structure with large refractive index (1.8). When the thickness of SiO x N y changes from 0.2 to 0.4 ¿m, the shape of transmission spectrum exhibits a large change. It was found that a higher transmission efficiency and narrower transmission peak was obtained in Au/SiO x N y /Au cascaded structure with a thin dielectric film (0.2 ¿m), with the increase of SiO x N y film's thickness, the transmission peak gradually widened and disappeared finally. This effect is useful in applications of biochemical sensing and tunable integrated plasmonic devices in the middle-infrared region.

关键词： Gold Refractive index Apertures Optical arrays Optical films Dielectrics Couplings Plasmons Shape Biomedical optical imaging

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Capacitance-voltage characterization of fully silicided gated MOS capacitor

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Journal of Semiconductors 2009年第3期30卷 46-51页

作者：王保民茹国平蒋玉龙屈新萍李炳宗刘冉 State Key Laboratory of ASIC and System Department of MicroelectronicsFudan University

This paper investigates the capacitance-voltage （C-V） measurement on fully silicided （FUSI） gated metal-oxide-semiconductor （MOS） capacitors and the applicability of MOS capacitor models. When the oxide leakage current of an MOS capacitor is large, two-element parallel or series model cannot be used to obtain its real C-V characteristic. A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used. We employed the threeelement and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors. The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion, while that extracted by the four-element model is close to the real capacitance, showing little frequency dispersion. The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program. We also investigated the influence of MOS capacitor＇s area on the measurement accuracy. The results indicate that the decrease of capacitor area can reduce the dissipation factor and improve the measurement accuracy. As a result, the frequency dispersion of the measured capacitance is significantly reduced, and real C-V characteristic can be obtained directly by the series model. In addition, this paper investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide. The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current, which is essential for the quasi-static C-V measurement. On the other hand, the photonic high-frequency C-V measurement can bypass the leakage problem, and get reliable low-frequency C-V characteristic, which can be used to evaluat

关键词： FUSI C-V photonic high-frequency C-V MOS capacitor model

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Characterization of Ultra-low k Porous Organosilica Thin Films

Characterization of Ultra-low k Porous Organosilica Thin Fil...

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2010 10th IEEE International Conference on Solid-state and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Shuang Fu Ke-Jia Qian Wei Zhang Shi-Jin Ding Zhong-yong Fan Department of Material Science Fudan University Shanghai 200433 China State Key Laboratory of ASI State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai Department of Material Science Fudan University Shanghai 200433 China

ISBN: (纸本)9781424457977

Porous organosilica thin films using 1,2-bis (triethoxysily)ethane, triethoxymethylsilane and a poly (ethylene oxide)-poly(propylene oxide)-poly (ethylene oxide) triblock copolymer template have been prepared by spin-on technique. The films were characterized by cross-sectional scanning electron microscopy, x-ray diffraction and Fourier-transform infrared spectroscopy. After thermal treatment at 350 ℃ in N2 for two hours, the films show well ordered porous structure as well as uniform and crack-free surface. The dielectric constant (k) as low as 2.0 was obtained at 100k Hz, and kept good thermal stability up to 500 ℃. Meanwhile, the resulting lowk porous films also exhibit low leakage current densities, e.g., 3.0×10-8 A/cm2 at 1 MV/cm, and good mechanical properties with elastic modulus of 4.7 GPa and hardness of 0.56 GPa in the case of 500 ℃ annealing.

关键词： Fourier transform infrared spectroscopy Porous thin films Pore structure heat treatment Elastic Modulus porous membrane Mechanical properties Soundness

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Applications of tunneling FET in memory devices

Applications of tunneling FET in memory devices

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International Conference on Solid-state and Integrated Circuit Technology

作者： Song-Gan Zang Xin-Yan Liu Xi Lin Lei Liu Wei Liu David Wei Zhang Peng-Fei Wang Walter Hansch State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai China Oriental Semiconductor Company Limited Suzhou China Institute for Physics Universitaet der Bundeswehr Muenchen Neubiberg Germany

ISBN: (纸本)9781424457977

Because of the special p-i-n structure of the tunneling FET (TFET), many different composite transistors can be formed with careful device design by combining TFET with MOSFET. In this paper, we propose the special applications of TFET as memory devices. A novel capacitor-less DRAM cell based on floating junction gate (FJG) concept can be configured with TFET. In addition, several different memory cells containing TFET will be discussed.

关键词： Logic gates Nonvolatile memory PIN photodiodes Random access memory system-on-a-chip MOSFET circuits Junctions

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Design and noise analysis of a fully-differential charge pump for phase-locked loops

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Journal of Semiconductors 2009年第10期30卷 126-131页

作者：宫志超卢磊廖友春唐长文 ASIC & System State Key Laboratory Fudan University Ratio Microelectronics Technology Co Ltd

A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is *** mismatch and current noise contribution from the CMFB circuit is *** order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling *** calculation result agrees well with the *** on the noise analysis,many methods to lower output current noise of the FDCP are *** fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm *** measured output reference spur is–64 dBc to–69 *** in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.

关键词： fully-differential charge pump mismatch noise common-mode feedback phase-locked loop

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An eighth order channel selection filter for low-IF and zero-IF DVB tuner applications

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Journal of Semiconductors 2009年第11期30卷 79-87页

作者：邹亮廖友春唐长文 ASIC & System State Key Laboratory Fudan University Ratio Microelectronics Technology Co Ltd

An eighth order active-RC filter for low-IF and zero-IF DVB tuner applications is presented, which is implemented in Butterworth biquad structure. An automatic frequency tuning circuit is introduced to compensate the cut-off frequency variation using a 6-bit switched-capacitor array. Switched-resistor arrays are adopted to cover different cut-off frequencies in low-IF and zero-IF modes. Measurement results show that precise cut-off frequencies at 2.5, 3, 3.5 and 4 MHz in zero-IF mode, 5, 6, 7 and 8 MHz in low-IF mode can be achieved, 60 dB frequency attenuation can be obtained at 20 MHz, and the in-band group delay agrees well with the simulation. Two-tone testing shows the in-band IM3 achieves -52 dB and the out-band IM3 achieves -55 dB with -11 dBm input power. This proposed filter circuit, fabricated in a SMIC 0.18μm CMOS process, consumes 4 mA current with 1.8 V power supply.

关键词： active-RC filter Butterworth frequency tuning group delay noise linearity

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Robust Low Voltage Program-Erasable Cobalt-Nanocrystal Memory Capacitors with Multistacked Al2O3/HfO2/Al2O3 Tunnel Barrier

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中国物理快报（英文版） 2009年第8期26卷 311-314页

作者： LIAO Zhong-Wei GOU Hong-Yan HUANG Yue SUN Qing-Qing DING Shi-Jin ZHANG Wei ZHANG Shi-Li State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai 200433 State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai 200433 School of Information and Communication KTH (Royal Institute of Technology) Electrum 229 SE-164 40 KistaSweden

An atomic-layer-deposited Al2O3/HfO2/Al2O3 (A/H/A) tunnel barrier is investigated for Co nanocrystal memory capacitors. Compared to a single Al2O3 tunnel barrier, the A/H/A barrier can significantly increase the hysteresis window, i.e., an increase by 9 V for ±12 V sweep range. This is attributed to a marked decrease in the energy barriers of charge injections for the A/H/A tunnel barrier. Further, the Co-nanocrystal memory capacitor with the A/H/A tunnel barrier exhibits a memory window as large as 4.1 V for 100 μs program/erase at a low voltage of ±7 V, which is due to fast charge injection rates, i.e., about 2.4 × 1016 cm−2s−1 for electrons and 1.9 × 1016 cm−2s−1 for holes.

关键词： No English keyword

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A 12-bit 100 MS/s pipelined ADC with digital background calibration

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Journal of Semiconductors 2009年第11期30卷 109-113页

作者：周立人罗磊叶凡许俊任俊彦 State Key Laboratory of ASIC & System Fudan UniversityMicroelectronics Science and Technology Innovation Platform

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.

关键词： pipelined analog-to-digital converter background calibration digital calibration capacitor mismatch finite op-amp gain

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A low-loss V-groove coplanar waveguide on an SOI substrate

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Journal of Semiconductors 2009年第7期30卷 51-53页

作者：赵宇航童家榕曾璇王勇 State Key Laboratory of ASIC & System Microelectronics Department Fudan University Shanghai IC Research and Development Center

A novel low-loss 50-Ω coplanar waveguide with V-groove on an SOI substrate is *** a CMOS-compatible process and anisotropic etching of silicon, surface silicon is removed from the *** measured results show that the V-groove coplanar waveguide causes about 50% less loss than the conventional one at a high frequency of up to 40 GHz.

关键词： SOI coplanar waveguide low loss radio frequency

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Boundary condition and initial value effects in the reaction-diffusion model of interface trap generation/recovery

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Journal of Semiconductors 2009年第7期30卷 70-75页

作者：罗勇黄大鸣刘文军李名复 State Key Laboratory of ASIC & System Department of Microelectronics Fudan University SNDL ECE Department National University of Singapore

A simple standard reaction-diffusion（RD） model assumes an infinite oxide thickness and a zero initial interface trap density, which is not the case in real MOS *** this paper, we numerically solve the RD model by taking into account the finite oxide thickness and an initial trap *** results show that trap generation/ passivation as a function of stress/recovery time is strongly affected by the condition of the gate-oxide/poly-Si *** an absorbent boundary is considered, the RD model is more consistent with the measured interfacetrap data from CMOS devices under bias temperature *** results also show that non-negligible initial traps should affect the power index n when a power law of the trap generation with the stress time, tn, is observed in the diffusion limited region of the RD model.

关键词： reaction-diffusion model interface-trap generation/passivation negative bias temperature instability charge pumping direct-current current-voltage

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