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Solving SAT problem by heuristic polarity decision-making algorithm

Science in China(Series F) 2007年第6期50卷 915-925页

作者： JING MingE ZHOU Dian TANG PuShan ZHOU XiaoFang ZHANG Hua State Key Laboratory of ASIC & System Microelectronics Department Fudan University Shanghai201203 China E. E. Department the University of Texas at Dallas TX 75083 USA

This paper presents a heuristic polarity decision-making algorithm for solving Boolean satisfiability （SAT）. The algorithm inherits many features of the current state-of-the-art SAT solvers, such as fast BCP, clause recording, restarts, etc. In addition, a preconditioning step that calculates the polarities of variables according to the cover distribution of Karnaugh map is introduced into DPLL procedure, which greatly reduces the number of conflicts in the search process. The proposed approach is implemented as a SAT solver named DiffSat. Experiments show that DiffSat can solve many ＂real-life＂ instances in a reasonable time while the best existing SAT solvers, such as Zchaff and MiniSat, cannot. In particular, DiffSat can solve every instance of Bart benchmark suite in less than 0.03 s while Zchaff and MiniSat fail under a 900 s time limit. Furthermore, DiffSat even outperforms the outstanding incomplete algorithm DLM in some instances.

关键词： SAT problem DPLL complete algorithm decision-making

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An offset voltage compensation ratio-capacitance bandgap voltage reference design for D/A converter

An offset voltage compensation ratio-capacitance bandgap vol...

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作者： He, Jing-Lan Min, Hao ASIC and System State Key Laboratory School of Information Science and Engineering Fudan University Shanghai 200433 China

ISBN: (纸本)9787561752289

Display devices need transfer digtal signals to analog signals. And Bandgap is a useful and important circuit for analog D/A converter design. This paper proposes a new bandgap voltage reference structure, which effectively reduces the power consumption of the circuit, improves the precision and compensates the offset voltage with ratio-capacit ance. The CMOS bandgap voltage reference is implemented in charter 0.35 μm n-well technology. Operating at an input voltage of 2 V, the bandgap has a very low power consumption of 8 μw, a DC power supply rejection ratio(PSRR) of 50 dB and a temperature coefficient of 30 ppm by simulation result.

关键词： Capacitance

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Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic

Robust Analog Circuit Sizing Using Ellipsoid Method and Affi...

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Asia and South Pacific Design Automation Conference

作者： Xuexin Liu Wai-Shing Luk Yu Song Pushan Tang Xuan Zeng ASIC & System State Key Laboratory Microelectronics Dept Fudan University Shanghai China

ISBN: (纸本)1424406293;9781424406296

Analog circuit sizing under process/parameter variations is formulated as a mini-max geometric programming problem. To tackle such problem, we present a new method that combines the ellipsoid method and affine arithmetic. Affine arithmetic is not only used for keeping tracks of variations and correlations, but also helps to determine the sub-gradient at each iteration of the ellipsoid method. An example of designing a CMOS operational amplifier is given to demonstrate the effectiveness of the proposed method. Finally numerical results are verified by SPICE simulation.

关键词： Robustness Analog circuits Ellipsoids Arithmetic Operational amplifiers Voltage Design optimization Constraint optimization Equations Educational programs

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A Novel reconfigurable VLSI architecture for motion estimation

A Novel reconfigurable VLSI architecture for motion estimati...

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International Conference on asic

作者： Cao Wei Hou Hui Lai Jin Mei Mao Zhi Gang Tong Jia Rong Min Hao State Key Laboratory of ASIC and System Fudan University Shanghai China Microelectronics Center Harbin Institute of Technology Harbin China

A new reconfigurable multi-BMA VLSI architecture was proposed to select different levels of trade-off between video quality, computing complexity and power for power aware applications. The architecture can reuse the smaller blocks' SADs to calculate 41 motion vectors of a 16times16 block in parallel for H.264's VBSME. TSMC 0.18 um CMOS technology was adopted and the circuit's power consumption can be changed between 13.8 and 247 mW with the typical algorithms. Under a clock frequency of 157 Mhz, the architecture allows the real-time processing of VGA at 30 fps with FS in a search range [-16, +15] at the high level.

关键词： Very large scale integration Motion estimation Computer architecture Energy consumption Image quality CMOS technology Circuits Clocks Frequency Switches

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Digital Correlation Demodulator Design for RFID Reader Receiver

Digital Correlation Demodulator Design for RFID Reader Recei...

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IEEE Conference on Wireless Communications and Networking

作者： Yuan Liu Chenling Huang Hao Min Guohong Li Yifeng Han Department of Microelectronics State Key Laboratory of ASIC & System Fudan University Shanghai China Mercury Technology (Shanghai) Company Limited Shanghai China

A high performance digital demodulator for RFID reader receiver is proposed. After carefully analyzing the characteristics of the received data, correlation operation is introduced into the demodulator to estimate the frequency of the received data and decode them. Simulation result indicates that this demodulator can work well under the 6dB input signal-to-noise ratio (SNR) with +/- 22% frequency deviation tolerance. FPGA implementation result shows that the communication distance between reader and tag can be extended to 5m above by the use of this demodulator.

关键词： Demodulation Radiofrequency identification Frequency estimation Field programmable gate arrays Decoding Frequency synchronization Signal processing Radio frequency Communications Society microelectronics

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An efficient transformation method for DFRM expansions

An efficient transformation method for DFRM expansions

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International Conference on asic

作者： H. Xu M. Yang L. Wang J.R. Tong A.E.A. Almaini Tianjin Vocational College of Mechanics and Electricity Tianjin China State Key Laboratory of ASIC & System Microelectronics Department Fudan University Shanghai China School of Engineering Napier University Edinburgh UK

Dual Form of Reed-Muller (DFRM) expansions with fixed polarity are derived from Reed-Muller (RM) expansions by using the operation of Kronecker matrix products. An efficient decomposition method is proposed based on the formulation. The method can be used for the transformation between from DFRM expansions to RM expansions within the same fixed polarity as well. Hence, the proposed method is bidirectional. After decomposition, the calculation of the duplicated matrix is avoided, resulting in less computation time. Time complexity of the algorithm is 0(2 1.5n ). The time used for small variables is virtual zero for the tested MCNC benchmarks. For large variable, it still works very well and achieves less than 20 seconds for 25-variable benchmark. In the implementation, only on-set coefficients are used. Consequently, the space complexity is O(M), where M is the number of on-set coefficients. It makes simultaneous optimization in both RM and DFRM expansions possible.

关键词： Circuit synthesis Circuit testing Logic testing Matrix decomposition Benchmark testing Electronic design automation and methodology Arithmetic Algebra Logic design Logic circuits

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Traffic Splitting with Network Calculus for Mesh Sensor Networks

Traffic Splitting with Network Calculus for Mesh Sensor Netw...

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International Conference on Future Generation Communication and Networking (FGCN)

作者： Huimin She Zhonghai Lu Axel Jantsch Li-Rong Zheng Dian Zhou ASIC & System State Key Laboratory Department of Microelectronics Fudan university Shanghai China Department of Electronic Computer and Software Systems Royal Institute of Technology Sweden

In many applications of sensor networks, it is essential to ensure that messages are transmitted to their destinations as early as possible and the buffer size of each sensor node is as small as possible. In this paper, we firstly propose a mesh sensor network system model. Based on this system model, the expressions for deriving the delay bound and buffer requirement bound are presented using network calculus. In order to balance traffic load and improve resource utilization, three traffic splitting mechanisms are proposed. The numerical results show that the delay bound and buffer requirement bound are lowered while applying those traffic splitting mechanisms. And thus the performance of the whole sensor network is improved.

关键词： Telecommunication traffic Calculus Traffic control Sensor systems Delay Wireless sensor networks Network topology Routing Packet switching Computer networks

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Parameterized model order reduction via a two-directional Arnoldi process

Parameterized model order reduction via a two-directional Ar...

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IEEE International Conference on Computer-Aided Design

作者： Yung-Ta Li Zhaojun Bai Yangfeng Su Xuan Zeng Department of Mathematics University of California Davis CA USA Department of Computer Science and Department of Mathematics University of California Davis CA USA School of Mathematical Sciences Fudan University Shanghai China ASIC & System State Key Laboratory Fudan University Shanghai China

This paper presents a multiparameter moment-matching based model order reduction technique for parameterized interconnect networks via a novel two-directional Arnoldi process. It is referred to as a PIMTAP algorithm, which stands for Parameterized Interconnect Macromodeling algorithm via a Two-directional Arnoldi Process. PIMTAP inherits the advantages of previous multiparameter moment-matching algorithms and avoids their shortfalls. It is numerically stable and adaptive, and preserves the passivity of parameterized RLC networks.

关键词： Integrated circuit interconnections Space technology Equations Mathematics Frequency Large-scale systems Reduced order systems Mathematical model Computer science Application specific integrated circuits

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Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-state Analysis of Nonlinear system with Process Variations

Stochastic Sparse-grid Collocation Algorithm (SSCA) for Peri...

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Asia and South Pacific Design Automation Conference

作者： Jun Tao Xuan Zeng Wei Cai Yangfeng Su Dian Zhou Charles Chiang ASIC & System State Key Laboratory Microelectronics Department Fudan University Shanghai China Department of Mathematics University of North Carolina Charlotte Charlotte NC USA Mathematics Department Fudan University Shanghai China Electrical Engineering Dept University of Texas Dallas Richardson TX USA Advanced Technology Group Synopsys Inc. Mountain View CA USA

ISBN: (纸本)1424406293;9781424406296

In this paper, stochastic collocation algorithm combined with sparse grid technique (SSCA) is proposed to deal with the periodic steady-state analysis for nonlinear systems with process variations. Compared to the existing approaches, SSCA has several considerable merits. Firstly, compared with the moment-matching parameterized model order reduction (PMOR), which equally treats the circuit response on process variables and frequency parameter by Taylor approximation, SSCA employs homogeneous chaos to capture the impact of process variations with exponential convergence rate and adopts Fourier series or wavelet bases to model the steady-state behavior in time domain. Secondly, contrary to stochastic Galerkin algorithm (SGA), which is efficient for stochastic linear system analysis, the complexity of SSCA is much smaller than that of SGA for nonlinear case. Thirdly, different from efficient collocation method, the heuristic approach which may results in "rank deficient problem" and "Runge phenomenon", sparse grid technique is developed to select the collocation points in SSCA in order to reduce the complexity while guaranteing the approximation accuracy. Furthermore, though SSCA is proposed for the stochastic nonlinear steady-state analysis, it can be applied for any other kinds of nonlinear system simulation with process variations, such as transient analysis, etc.

关键词： Stochastic systems Steady-state Algorithm design and analysis Nonlinear systems Circuits Frequency Chaos Convergence Fourier series Wavelet domain

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Characterization of Al2O3 Thin Films on GaAs Substrate Grown by Atomic Layer Deposition

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Chinese Physics Letters 2006年第7期23卷 1929-1931页

作者：卢红亮李彦波徐敏丁士进孙亮张卫汪礼康 State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai 200433 College of Electronic and Information Engineering Hebei University Baoding 071002

Al2O3 thin films are grown by atomic layer deposition on GaAs substrates at 300℃. The structural properties of the Al2O3 thin film and the Al2O3/GaAs interface are characterized using x-ray diffraction （XRD）, high- resolution transmission electron microscopy （HRTEM）, and x-ray photoelectron spectroscopy （XPS）. The XRD results show that the as-deposited Al2O3 film is amorphous. For 30 atomic layer deposition growth cycles, the thicknesses of the Al2O3 thin film and the interface layer from the HRTEM are 3.3 nm and ***, respectively. XPS analyses reveal that the Al2O3/GaAs interface is almost free from As2O3.

关键词： Characterization Al2O3 Thin Films GaAs Substrate Grown Atomic Layer Deposition

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