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Proceedings of the 60th Annual ACM/IEEE Design Automation Conference

作者： Jinxin Zhang Jiarui Bao Zhangcheng Huang Xuan Zeng Ye Lu State Key Lab. of ASIC & System School of Information Science and Technology Frontier Institute of Chip and System State Key Lab. of ASIC & System Microelectronics Department Fudan University Shanghai China

ISBN: (纸本)9798350323481

Despite the effort of analog circuit design automation, currently complex analog circuit design still requires extensive manual iterations, making it labor intensive and time-consuming. Recently, reinforcement learning (RL) algorithms have been demonstrated successfully for the analog circuit design optimization. However, a robust and highly efficient RL method to design analog circuits with complex design space has not been fully explored yet. In this work, inspired by multiagent planning theory as well as human expert design practice, we propose a multiagent based RL (MA-RL) framework to tackle this issue. Particularly, we (i) partition the complex analog circuits into several sub-blocks based on topology information and effectively reduce the complexity of design search space; (ii) leverage MA-RL for the circuit optimization, where each agent corresponds to a single sub-block, and the interactions between agents delicately mimic the best design tradeoffs between circuit sub-blocks by human experts; (iii) introduce the multiagent twin-delayed techniques to further boost training stability and accomplish higher performances. Experiments on two different analog circuit topologies and knowledge transfers between two technology nodes are demonstrated. It's shown that MA-RL framework can achieve the best FoM for complex analog circuits design. This work shines the light for future large scale analog circuit system design automation.

关键词： complex analog circuits

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Routability-Driven Macro Placement Engine for Modern FPGAs With Complex Cascade Shape and Region Constraints

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems 2025年

作者： Gu, Hao Gu, Jian Peng, keyu Chen, Jianli Yang, Jun Zhu, Ziran Southeast University National ASIC System Engineering Research Center School of Integrated Circuits Nanjing210096 China Fudan University State Key Lab of ASIC and System Shanghai200433 China

Field-programmable gate array (FPGA) macro placement holds a crucial role within the FPGA physical design flow since it substantially influences the subsequent stages of cell placement and routing. With the increasing number of macros and the complex cascade shape and region constraints imposed by modern FPGAs, the routability and macro placement have become much more challenging. In this paper, we propose an effective and efficient routability-driven macro placement algorithm for modern FPGAs with cascade shape and region constraints. To reserve adequate space for cell placement and guarantee routability, we first develop a routability-driven mixed-size analytical global placement that evenly distributes both macros and cells while considering cascade shape and region constraints. Particularly, the proposed global placement engine integrates a well-trained congestion prediction model, targeting benchmarks with high routing congestion to enhance overall routability. Then, we propose an integer linear programming (ILP)-based cascade shape legalization followed by matching-based macro legalization to remove macro overlaps while satisfying the region constraints. Finally, a routability-driven detailed macro placement is proposed to refine the solution. Compared with the winners of the MLCAD 2023 FPGA macro placement contest and state-of-the-art works, experimental results show that our algorithm achieves the best overall score and routability. © 1982-2012 IEEE.

关键词： Electronic design automation

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The Power of Graph Signal Processing for Chip Placement Acceleration 24

The Power of Graph Signal Processing for Chip Placement Acce...

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43rd International Conference on Computer-Aided Design, ICCAD 2024

作者： Liu, Yiting Zhou, Hai Wang, Jia Yang, Fan Zeng, Xuan Shang, Li School of Computer Science Fudan University Shanghai China Department of ECE Northwestern University Evanston United States Department of ECE IIIinois Institute of Technology Chicago United States State Key Lab of ASIC & System Microelectronics Department Fudan University Shanghai China

ISBN: (纸本)9798400710773

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multi-resolution smooth signals of circuit graphs to generate optimized placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Experimental results show that GiFt significantly improving placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, compared to DREAMPlace, the recently proposed GPU-accelerated analytical placer, GF-Placer improves total runtime over 45%. © 2024 Copyright is held by the owner/author(s).

关键词： Nonlinear programming

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Thermal Stability of Reliable Polycrystalline Zirconium Oxide for Nonvolatile Memory Application

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Chinese Physics Letters 2008年第10期25卷 3742-3745页

作者：周鹏李晶陈良尧汤庭鳌林殷茵 School of Microelectronies and State Key Lab of ASIC and System Fudan University Shanghai 200433 Department of Optical Science and Engineering Fudan University Shanghai 200433

Thermal stability of resistive switching of stoichiometric zirconium oxide thin films is investigated for high yielding nonvolatile memory application. The A1/ZrO2/AI cell fabricated in the conventional device process shows highly reliable switching behaviour between two distinct stable resistance states. The retention capabilities are also tested under various conditions and temperatures. The excellent performance of Ai/ZrO2/AI ceil can be explained by assuming that anode/ZrO2 interface exists and by conducting filament forming/rupture mechanism. The device failure is illustrated in terms of permanent conducting filaments formation.

关键词： the power-law exponents precipitation durative abrupt precipitation change

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The Power of Graph Signal Processing for Chip Placement Acceleration

arXiv

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arXiv 2025年

关键词： Nonlinear programming

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Polarity-Free Resistive Switching Characteristics of CuxO Films for Non-volatile Memory Applications

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Chinese Physics Letters 2008年第3期25卷 1087-1090页

作者：吕杭炳周鹏傅秀峰尹明宋雅丽唐立汤庭鳌林殷茵 School of Microelectronics and State Key Lab of ASIC & System Fudan University Shanghai 200433

Resistive switching characteristics of CuxO films grown by plasma oxidation process at room temperature are investigated. Both bipolar and unipolar stable resistive switching behaviours are observed and confirmed by repeated current voltage measurements. It is found that the RESET current is dependent on SET compliance current. The mechanism behind this new phenomenon can be understood in terms of conductive filaments formation/rupture with the contribution of Joule heating.

关键词： supernova explosion proto-neutron star shock wave

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Design and simulation of a standing wave oscillator based PLL

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Frontiers of Information Technology & Electronic Engineering 2016年第3期17卷 258-264页

作者： Wei ZHANG You-de HU Li-rong ZHENG State Key Lab of ASIC & System Fudan University Pack Vinn Excellence Center School of ICTRoyal Institute of Technology (KTH) Eletrum 229

A standing wave oscillator(SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor(IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop(PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P9 M complementary metal-oxide-semiconductor(CMOS) technology, and can be used directly in a high performance multi-core microprocessor.

关键词： Standing wave oscillator （SWO） Clock distribution Phase locked loop （PLL） Varactor

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Observation of Contact Resistivity Independence from Schottky Barrier Height on Heavily Doped P-type SiGe 13

Observation of Contact Resistivity Independence from Schottk...

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2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Jian Zhang H.Yu M Schaekers N.Horiguchi Lin-Lin Wang Yu-Long Jiang State Key Lab of ASIC and System School of Microelectronics Fudan University Imec

ISBN: (纸本)9781467397209

The electrical characteristics of Ti/p-Si Ge contacts with Ti thicknesses of 3nm and 5nm have been investigated in this paper. Ti N was used as a cap layer on Ti. It is observed that as Ti film becomes thinner, Ti/pSi Ge contact resistivity(ρ) increases, but its Schottky barrier height(SBH) decreases, which does not coincide with the regular ρc-SBH dependence. Using Ti N/p-Si Ge as a control sample, it is concluded that when Ti film is thinned down to nm scale, the contact property is strongly influenced by Ti N cap layer.

关键词： Estimation Field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Dual Multimodal Fusions with Convolution and Transformer Layers for VLSI Congestion Prediction

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems 2024年第6期44卷 2378-2391页

作者： Gu, Hao Wang, Youwen Zheng, Xinglin Peng, keyu Zhu, Ziran Chen, Jianli Yang, Jun The National ASIC System Engineering Research Center School of Integrated Circuits Southeast University Nanjing210096 China The State Key Lab of ASIC & System Fudan University Shanghai200433 China

In very large scale integration (VLSI) circuit physical design, precise congestion prediction during placement is crucial for enhancing routability and accelerating design processes. Existing congestion prediction models often encounter challenges in handling multimodal information and lack effective fusion of placement and netlist features, limiting their prediction accuracy. In this paper, we present a novel congestion prediction model that leverages dual multimodal fusions with convolution and transformer layers to effectively capture the multiscale placement information and enhance congestion prediction accuracy. We first adopt convolutional neural networks (CNN) to extract grid-based placement features and heterogeneous graph convolutional networks (HGCN) to extract netlist information. To help the model understand the correlation between different modalities, we then propose an early feature fusion (EFF) to integrate netlist knowledge into multiscale placement features at multimodal interaction subspace. Besides, a deep feature fusion (DFF) method is proposed to further fuse multimodal features, which has multiple vision transformer layers based on adaptive attention enhancement technology. These layers include self-attention to boost intra-modal features and cross-attention to perform cross-modal feature fusion on netlist and grid-based placement features. Finally, the output features of DFF are sent into the cascaded decoder to recover the congestion map by exploiting several upsampling layers and merging with EFF features. Compared with the existing state-of-the-art congestion prediction models, experimental results demonstrate that our model not only outperforms them in prediction accuracy, but also excels in reducing routing congestion when integrated into the placer DREAMPlace. © 1982-2012 IEEE.

关键词： VLSI circuits

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Design memristor-based computing-in-memory for AI accelerators considering the interplay between devices, circuits, and system

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Science China(Information Sciences) 2023年第8期66卷 243-253页

作者： Junjie AN Linfang WANG Wang YE Weizeng LI Hanghang GAO Zhi LI Zhidao ZHOU Jinghui TIAN Jianfeng GAO Chunmeng DOU Qi LIU School of Microelectronics University of Science and Technology of China State key Lab of Fabrication Technologies for Integrated Circuits Institute of MicroelectronicsChinese Academy of Sciences School of Microelectronics University of Chinese Academy of Sciences Frontier Institute of Chip and System State Key Laboratory of ASIC and System Fudan University

Recent advances in developing beyond von Neumann architectures have moved the memristive devices to the forefront as one of the key enablers to realizing memristive computing-in-memory(m CIM)structures, which shows a great promise to boost the energy-efficiency and the performance of artificial intelligence(AI) chips. In this study, by considering the interactions between devices, circuits, and systems in the m CIM design, we propose several cross-layer design techniques, including(1) the BL-SL interactive forming protection(BSIFP) circuit that can reduce the voltage drop on the selected transistor, suppress the current overshoot by 65.96%, and improve the bit-cell density by more than 10.19%,(2) the clamping transistor trimming scheme(CTTS) to prevent the multiply-and-accumulate(MAC) signal margin degradation from chip-to-chip resistance variations, and(3) dynamic input-parallelism and output-precision(DIPOP) that can reduce the energy cost by 22.92% in a typical inference task with negligible accuracy loss. The results demonstrate the significant role of the cross-layer-interactive approach and provide a preliminary guideline for highly-efficient m CIM design.

关键词： memristor resistive memory computing-in-memory artificial intelligence cross-layer co-design

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