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检索条件"机构=School of Microelectronies and State Key Lab of ASIC and System"

共 181 条记录，以下是101-110 订阅

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An ultra-low quiescent current output capacitor-less low-dropout regulator with a novel slew-rate-enhanced circuit

An ultra-low quiescent current output capacitor-less low-dro...

引用

IEEE International Workshop on Radio-Frequency Integration Technology (RFIT)

作者： Yang Chen Yizhong Yang Longjie Du Guangjun Xie Xin Cheng Maoxiang Yi School of Electronic Science and Applied Physics Hefei University of Technology Hefei China State Key Lab of ASIC and System Fudan University Shanghai China

This paper presents an ultra-low quiescent current output capacitor-less Low-dropout (LDO) regulator with a novel slew-rate-enhanced (SRE) circuit. By adopting the novel SRE circuit, the transient response of the regulator was improved apparently. Simulation results show that, the LDO regulator consumes a quiescent current of only 930nA at steady state.

关键词： Regulators Transient response Stability analysis Logic gates Circuit stability Simulation Transient analysis

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A biologically-inspired network for generic object recognition using CUDA

A biologically-inspired network for generic object recogniti...

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2009 11th IEEE International Conference on e-Health Networking, Applications and Services, Healthcom 2009

作者： Wang, Yuekai Wu, Xiaofeng Song, Xiaoying Zhang, Wenqiang Weng, Juyang State Key Lab. of ASIC and System Fudan University Shanghai 200433 China Department of Electronic Engineering Fudan University Shanghai 200433 China School of Computer Science Fudan University Shanghai 200433 China Dept. of Computer Sci. and Eng. Michigan State University East Lansing MI 48824 United States

Generic object recognition is one of the most important fields in the artificial intelligence. Some cortex-like networks for generic object recognition are proposed these years. But most of them concentrated on the discussion about the recognition performance (such as recognition rate, number of objects to be recognized), not the practicability, i.e., implementation with ubiquitous devices and application in real time. This paper reports a try on implementation of a biologically-inspired where-what network (WWN), which integrates object recognition and attention in a single network, via parallelizing the various stages of the network training with CUDA on GPU to shorten the training time. The experiment on HAIBAO Robot exhibited in 2010 Shanghai Expo shows that this optimization can achieve a speedup of almost 16 times compared to the C-based program on an Intel Core 2 DUO 3.00 GHZ CPU in real environments. © 2012 Springer-Verlag GmbH.

关键词： Object recognition

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Exact Minimization of Large Fixed Polarity Dual Form of Reed-Muller Functions

Exact Minimization of Large Fixed Polarity Dual Form of Reed...

引用

2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： M.Yang H.Xu L.Wang J.R.Tong A.E.A.Almaini State Key Lab of ASIC ＆ System Microelectronics Dept.Fudan University Tianjin Vocational College of Mechanics and Electricity School of Engineering Napier University

ISBN: (纸本)1424401607

Dual Form of Reed-Muller（DFRM） expansions are implemented in OR/XNOR logic,which are based on the features of coincidence operation and known as fixed polarity Canonical OR-Coincidence（COC） expansions. An efficient minimization method is proposed to find the best polarity COC expansion for large *** method derives one expansion from another adjacent polarity expansion using gray code,resulting in small space complexity O（M） and time complexity O（2~nM/ogM）(n and M are the number of input variables and the number of on-set COC maxterms).Hence,it makes minimization for large functions practical.

关键词： Logic Synthesis Optimization Dual Form of Reed-Muller EDA

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Automated and Agile Design of Layout Hotspot Detector via Neural Architecture Search

Automated and Agile Design of Layout Hotspot Detector via Ne...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Zihao Chen Fan Yang Li Shang Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University Shanghai China China and Shanghai Key Laboratory of Data Science School of Computer Science Fudan University Shanghai China

This paper presents a neural architecture search scheme for chip layout hotspot detection. In this work, hotspot detectors, in the form of neural networks, are modeled as weighted directed acyclic graphs. A variational autoencoder maps the discrete graph topological space into a continuous embedding space. Bayesian Optimization performs neural architecture search in this embedding space, where an architecture performance predictor is employed to accelerate the search process. Experimental studies on ICCAD 2012 and ICCAD 2019 Contest benchmarks demonstrate that, the proposed scheme significantly improves the agility of previous neural architecture search schemes, and generates hotspot detectors with competitive detection accuracy, false alarm rate, and inference time.

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Unijunction Transistor on Silicon-On-Insulator Substrate 15

Unijunction Transistor on Silicon-On-Insulator Substrate

引用

15th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2020

作者： Chen, Y.X. Liu, J. Xiao, K. Zaslavsky, A. Cristoloveanu, S. Liu, F.Y. Li, B. Wan, J. State Key Lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China Brown University Department of Physics and School of Engineering ProvidenceRI02912 United States IMEP-LAHC INP-Grenoble/Minatec CS 50257 Grenoble38016 France Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China

ISBN: (纸本)9781728162355

A unijunction transistor based on fully-depleted silicon-on-insulator substrate is proposed. The device structure is similar to a junction field effect transistor. By conducting the TCAD simulation, we observe sharp switching and large hysteresis in emitter current-emitter voltage curves with the turn-on voltage linearly controlled by the second base voltage. The operation of the device is mainly determined by the emitter-channel PN junction, which is induced by the backgate voltage. The impact of the backgate voltage on the electrical characteristics is analyzed by changes in the channel potential. © 2020 IEEE.

关键词： Silicon on insulator technology

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TOTAL: Topology Optimization of Operational Amplifier via Reinforcement Learning

TOTAL: Topology Optimization of Operational Amplifier via Re...

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IEEE International Symposium on Quality Electronic Design

作者： Zihao Chen Songlei Meng Fan Yang Li Shang Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University Shanghai China China and Shanghai Key Laboratory of Data Science School of Computer Science Fudan University Shanghai China

With ever-increasing design complexity and stringent time-to-market pressure, automated topology synthesis tools for operational amplifiers are required to produce designs meeting different specifications. This paper proposes TOTAL, a reinforcement learning-based topology optimization method for operational amplifiers. We decompose the circuit topology design as a Markov decision process to solve the high dimensionality of the design space, with the three-stage cascode paradigm fixed to avoid meaningless structures. Therefore, starting from a basic behavior-level topology, an agent modifies the circuit step by step. Specifically, this agent mainly adopts a graph neural network to understand each design state, including specifications and the design history, and a convolutional neural network to modify the current topology. Every completed circuit is then simulated and evaluated by a customized reward function to guide the agent in finding qualified circuits, among which only the optimal one ever recorded is mapped to the transistor level for further evaluation. Experimental results show that the trained agent can not only generate high-performance circuits, but also be reusable by transferring to other specifications as a pre-trained model and achieving competitive results.

关键词： Operational amplifiers Circuit topology Network topology Optimization methods Reinforcement learning Markov processes Topology

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Skull-closed autonomous development: Object-wise incremental learning

Skull-closed autonomous development: Object-wise incremental...

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9th International Symposium on Neural Networks, ISNN 2012

作者： Wang, Yuekai Wu, Xiaofeng Weng, Juyang State Key Lab. of ASIC and System Fudan University Shanghai 200433 China Department of Electronic Engineering Fudan University Shanghai 200433 China School of Computer Science Fudan University Shanghai 200433 China Dept. of Computer Sci. and Eng. Michigan State University East Lansing MI 48824 United States

ISBN: (纸本)9783642313455

The series of Where-What Networks (WWNs) is a brain-inspired developmental model that simulates the dorsal (where) stream and the ventral (what) stream that converge to the motor area in the frontal cortex. Since developmental learning is always incremental, the order of different stimuli should affect the outcome of learning. In contrast to the uniform distribution of stimuli across image frames used in prior WWN experiments, this work studies non-uniform distribution in the sense that during training one object is presented at all the image locations before another object is presented. A new mechanism called cell regenesis is introduced to enable a less-often used cell to recommit its neuronal resource to new stimuli. The experimental results shown in this paper indicate that WWN-6 can deal with object-wise incremental learning. © 2012 Springer-Verlag.

关键词： Computer vision

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eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symmetric Sparse Matrix-Vector Multiplication

eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symm...

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： Ruiqi Chen Haoyang Zhang Yuhanxiao Ma Jianli Chen Jun Yu Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China Gallatin School of Individualized Study New York University New York USA

Symmetric Sparse Matrix-Vector Multiplication (SSpMV) is a prevalent operation in numerous application domains (e.g., physical simulations, machine learning, and graph processing). Existing researches focus on the SSpMV implementation and its improvement on high-performance computing platforms but ignore the resource-limited edge platforms due to the main challenges: memory access overload and limited computing parallelism feasibility. To this end, this paper proposes an embedded-FPGA-based hardware accelerator for SSpMV, called eSSpMV. We first propose an optimized data format, named Symmetric Compressed Sparse Row (SCSR), to reduce memory consumption. Moreover, a fully-pipelined computation unit is proposed to be compatible with the optimized data format. Experimental results show that eSSpMV outperforms the state-of-the-art FPGA implementation for 2.9 x speedup, while still achieving a computing resource reduction of 39.3% and 32.3% for LUT and DSP, respectively. As for edge CPU and GPU implementations, eSSpMV achieves 9.3x speedup over CPU while acquiring 13.1 x better power latency product than GPU.

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Advanced MOSFET Model Based on Artificial Neural Network

Advanced MOSFET Model Based on Artificial Neural Network

引用

China Semiconductor Technology International Conference (CSTIC)

作者： JH. Wei W. Mao H. Fang Z. Zhang JX. Zhang BJ. Lan J. Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China Suzhou Foohu Technology Co. Ltd.

ISBN: (数字)9781728165585

ISBN: (纸本)9781728165592

In this work, we develop a novel MOSFET model for circuit simulation purpose. Instead of using traditional physics-driven model, such as BSIM model, our work uses ANN to model the electrical behavior of the transistor. With unique pre and post-processing procedures, the ANN is trained to model the drain current precisely under various applied voltage, device size and temperature. The model is further successfully implemented in SPICE through Verilog-A language. Both n-type and p-type MOSFETs show good fitting between the BSIM and ANN models. Eventually, an inverter and ring oscillator based on ANN model are demonstrated with static and transient simulations, showing good agreement with the results from BSIM model.

关键词： Semiconductor device modeling Ring oscillators MOSFET Fitting Artificial neural networks Inverters Integrated circuit modeling

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HierSyn: Fast Synthesis for Large Hierarchical Designs

HierSyn: Fast Synthesis for Large Hierarchical Designs

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International Conference on asic

作者： Yishan Zhang Zhiyong Zhang Chang Wu School of Microelectronics State-Key Lab of ASIC and System Fudan University Shanghai China Shanghai Fudan Microelectronics Group Co. Ltd Shanghai China

As design goes into multi-billion transistors, the synthesis runtime becomes an important issue, particularly for design verification and prototyping, as one may run the synthesis many times with design change. Module-by-module synthesis with multi-threading is a natural solution for fast synthesis, however, at the cost of quality of results (QoR) degradation. Besides, multi-thread speedup may not be so good due to very uneven sizes of the modules. In this paper, we propose a design hierarchy restructuring based multi-thread synthesis algorithm for large-scale designs. Small module flattening and large module partitioning are used to create moderate size design modules. Our experimental results show that our algorithm can produce results within 3% area increase and 21.3x speedup over the flat synthesis flow.

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