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作者： Lu, Bing-Rui Li, Jin-Xing Guo, Hong-Bin Gao, Chen Huq, Ejaz Qu, Xin-Ping Chen, Yifang Liu, Ran State Key Lab of ASIC and System Fudan University No. 220 Handan Rd. Shanghai 200433 China Micro and Nanotechnology Centre Rutherford Appleton Laboratory Chilton Didcot Oxfordshire OX11 0QX United Kingdom School of Microelectronics Fudan University 220 Handan Road Shanghai China

In this paper, we present a novel fabrication technique for constructing light focusing lenses, dielectric Fresnel zone plates on both flat wafers and tips of plastic optical fibers (POFs). SU-8 zone plate structures are made on glass substrate by photolithography with ink-printed soft mask, and then used as the template for hot embossing on the tip of PMMA POF. Focusing behavior for both 472 and 633 nm laser beams and LEDs in different colors are observed on glass wafers and POF tips, indicating that the proposed dielectric Fresnel zone plates can be built onto both substrate by a direct hot embossing process which may lead to a high volume production at low cost. Light intensity measurement on POFs proves that light focusing is achieved while intensity is maintained. This structure is expected to have broad applications in micro-imaging, micro-focusing as well as point-of-care medical surgeries. © 2011 Elsevier B.V. All rights reserved.

关键词： Glass

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High Efficient Automatic Power/Ground Layout Routing Algorithm for Analog ICS

High Efficient Automatic Power/Ground Layout Routing Algorit...

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China Semiconductor Technology International Conference (CSTIC)

作者： Jiaxin. Zuo Fei. Li Jing. Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China Suzhou Foohu Technology Co. Ltd.

In this work, we explored an efficient automatic layout routing algorithm for connecting the power and ground pins in analog integrated circuits. A rectilinear minimal spanning tree (RMST) algorithm for two sets of pins is developed, in which minimal spanning tree is used to form the initial connections between pins. The obstacle-avoiding maze routing algorithm is used to break and reconnect the power and ground nets to avoid any short circuit. The genetic algorithm (GA) is further introduced to optimize the total connection wirelength. We also expanding the wire width to avoid electromigration and IR-drop.

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A Mixed-Variable Bayesian Optimization Approach for Analog Circuit Synthesis

A Mixed-Variable Bayesian Optimization Approach for Analog C...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Jialin Lu Shuhan Zhang Fan Yang Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A.

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

Bayesian Optimization (BO) is an efficient method for black-box optimization problems. It has been successfully applied to the analog circuit sizing problem. However, all the design variables are viewed as continuous variables in these methods. Actually, many design variables are discrete due to the design rules. In this paper, we proposed an improved BO method for analog circuit sizing with both discrete and continuous variables. We also utilize the Gaussian Process (GP) regression model as the surrogate model for BO. However, we modified the kernel of GP and make it applicable to mixed variables. Experimental results demonstrated that the proposed mixed-variable BO method can significantly reduce the number of simulations with comparable optimization results, compared with the existing BO methods.

关键词： Optimization Analog circuits Kernel Linear programming Bayes methods Integrated circuit modeling Gaussian processes

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Pattern transfer of nano-scale ferroelectric PZT gratings by a reversal nanoimprint lithography

Pattern transfer of nano-scale ferroelectric PZT gratings by...

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作者： Li, Zhi-Dong Shen, Zhen-Kui Hui, Wen-Yuan Qiu, Zhi-Jun Qu, Xin-Ping Chen, Yi-Fang Liu, Ran State Key Lab of Asic and System Department of Microelectronics Fudan University Shanghai 200433 China Rutherford Appleton Laboratory STFC Chilton Didcot Oxon OX11 0QX United Kingdom Micro and Nanotechnology Centre United Kingdom School of Microelectronics Fudan University 220 Handan Road Shanghai China

Nanoscale PZT gratings are successfully transferred to a Pt substrate using reversal nanoimprint technique without any chemical etch processes. The transfer process is preliminarily studied by measuring the surface topography of PZT coated on templates before transferring as well as the transferred patterns on substrates. Piezoelectric force microscopy (PFM) and Raman spectroscopy are used to investigate the transferred PZT nanostructures after annealing. Good ferroelectric and structural properties have been demonstrated by the transferred PZT nanostructures, indicating that this reversal imprint technique is applicable for forming nanoscale PZT domains, which may lead to the manufactures of high density data storage devices at economic cost. © 2011 Elsevier B.V. All rights reserved.

关键词： Nanoimprint lithography

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An efficient asynchronous batch Bayesian optimization approach for analog circuit synthesis

arXiv

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arXiv 2021年

作者： Zhang, Shuhan Yang, Fan Zhou, Dian Zeng, Xuan State Key Lab of ASIC & System School of Microelectronics Fudan University Shanghai China Department of Electrical Engineering University of Texas at Dallas RichardsonTX United States

In this paper, we propose EasyBO, an Efficient ASYnchronous Batch Bayesian Optimization approach for analog circuit synthesis. In this proposed approach, instead of waiting for the slowest simulations in the batch to finish, we accelerate the optimization procedure by asynchronously issuing the next query points whenever there is an idle worker. We introduce a new acquisition function which can better explore the design space for asynchronous batch Bayesian optimization. A new strategy is proposed to better balance the exploration and exploitation and guarantee the diversity of the query points. And a penalization scheme is proposed to further avoid redundant queries during the asynchronous batch optimization. The efficiency of optimization can thus be further improved. Compared with the state-of-the-art batch Bayesian optimization algorithm, EasyBO achieves up to 7.35× speed-up without sacrificing the optimization results. © 2021, CC BY-NC-SA.

关键词： Timing circuits

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A systematic Investigation of TiN/CuxO/Cu RRAM with Long Retention and Excellent Thermal Stability

A Systematic Investigation of TiN/CuxO/Cu RRAM with Long Ret...

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IEEE International Memory Workshop (IMW)

作者： P. Zhou H. J. Wan Y. L. Song M. Yin H. B. Lv Y. Y. Lin S. Song R. Huang J. G. Wu M. H. Chi State Key Lab of ASIC & System and School of Microelectronics Fudan University Shanghai China Memory Technology Development Center Semiconductor Manufacturing International Corporation Shanghai China

ISBN: (纸本)9781424437627

The long retention, more than 10 years at 85degC, and excellent thermal reliability memory of TiN-Cu x O-Cu (with TiN cap layer as top electrode) is reported. TiN cap layer results in more stable reset from low resistance state (LRS) to high resistance state (HRS) under positive pulse and SET under negative pulse, which is beneficial for providing large programming current or voltage on the resistive random access memory (RRAM) resistor connected in series with a select transistor. Results show that the structure of TiN-Cu x O-Cu with its compatibility to CMOS technology appears a promising memory device for embedded application.

关键词： Tin Thermal stability Voltage Temperature Fabrication Electrodes Plasma measurements Sputtering Pulse measurements CMOS technology

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Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network

Efficient Performance Trade-off Modeling for Analog Circuit ...

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IEEE International Conference on Computer-Aided Design

作者： Zhengqi Gao Jun Tao Fan Yang Yangfeng Su Dian Zhou Xuan Zeng ASIC & System State Key Lab School of Microelectronics Fudan University Shanghai China School of Mathematical Sciences Fudan University Shanghai China University of Texas at Dallas Dallas USA

In this paper, we propose an efficient performance trade-off modeling method for analog circuit based on Bayesian Neural Network (BNN). First, we use a single BNN to simultaneously model multiple performances of interest (PoIs) of an analog circuit. This BNN model can be trained by using a novel automatic differential variational inference (ADVI) method with affordable computational cost. Next, the performance trade-off model can be extracted by embedding BNN into Bayesian optimization framework combined with a modified multi-objective evolutionary method. Since the correlations among different PoIs are implicitly encoded in the BNN model, the proposed method can capture the performance trade-off model efficiently and accurately. The numerical experiments demonstrate that compared to the state-of-the-art algorithms, the proposed method can achieve up to 2× runtime reduction without surrendering any accuracy.

关键词： Computational modeling Analog circuits Pareto optimization Integrated circuit modeling Bayes methods Neural networks

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Analytic model for subthreshold channel potential and threshold voltage of the Schottky-barrier surrounding-gate MOSFETS

Analytic model for subthreshold channel potential and thresh...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Guang-Xi Hu Shu-Yan Hu Pei-Cheng Li Ran Liu Ling-Li Wang Xing Zhou ASIC and System State Key Lab Fudan University Shanghai P. R. China School of Electrical & Electronic Engineering Nanyang Technological University Singapore

ISBN: (纸本)9781479932849

The threshold voltage, V th , of a surrounding-gate (SG) Schottky-barrier (SB) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. An analytical expression for surface potential is obtained by solving Poisson's equation. Based on the potential model, an analytical expression for V th is achieved, with quantum mechanical effects and SB lowering effect included. It is found that V th will be raised by quantum mechanical effects and lowered by SB lowering effect. It is also found that, the influence of channel length on V th is complicated; when the channel length is 20 nm, V th is the smallest.

关键词： MOSFET Electric potential Semiconductor device modeling Silicon Analytical models Quantum mechanics Logic gates

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Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process

Bayesian Optimization Approach for Analog Circuit Design Usi...

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IEEE International Symposium on Circuits and systems

作者： Jiangli Huang Shuhan Zhang Cong Tao Fan Yang Changhao Yan Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A

ISBN: (纸本)9781728192017;9781728192024

In this paper, we propose an efficient Bayesian optimization approach for analog circuit synthesis based on the multi-task Gaussian process model. Instead of building the Gaussian process models separately for each circuit specification as the traditional Bayesian optimization methods do, we extend the Gaussian process to a vector-valued function with a shared covariance function to learn the dependencies between different specifications of circuits. The weighted expected improvement function is selected as the acquisition function to cope with the constraints. The experimental results show that the proposed method can reduce the number of simulations while achieving better optimization results.

关键词： Correlation Circuits and systems Optimization methods Gaussian processes Analog circuits Bayes methods Circuit synthesis

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Silicon nanowires by combined nanoimprint and angle deposition for gas sensing applications

Silicon nanowires by combined nanoimprint and angle depositi...

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作者： Gao, Chen Xu, Zhen-Cheng Deng, Shao-Ren Wan, Jing Chen, Yifang Liu, Ran Huq, Ejaz Qu, Xin-Ping State Key Lab of ASIC and System Department of Microelectronics Fudan University Shanghai 200433 China Rutherford Appleton Laboratory Chilton Didcot Oxon OX11 0QX United Kingdom Nanoscience and Nanotechnology Micro and Nanotechnology Centre United Kingdom School of Microelectronics Fudan University 220 Handan Road Shanghai China

In this work, we demonstrate the fabrication of silicon nanowires, with their widths ranging from 22 nm to 110 nm, using the combination of bilayer nanoimprint and angle deposition. The approach makes the widths of the nanowires adjustable, offering an alternative solution for high-resolution, low-cost, and high-throughput fabrication of nanowire sensors. Using this approach, silicon nanowires with different widths are formed on the boron-doped top Si layers of the SOI substrates, and are used as sensing parts of the gas sensors. The Si nanowire sensors with wire widths of 60 nm and 90 nm demonstrate relative sensitivities of 155% and 44% to the testing gas of NO2. © 2011 Elsevier B.V. All rights reserved.

关键词： Nanowires

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