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Design Automation Conference

作者： Yan Li Xiaoyoung Zeng Zhengqi Gao Liyu Lin Jun Tao Jun Han Xu Cheng Mehdi Tahoori Xiaoyang Zeng State Key Lab. ASIC & System School of Microelectronics Fudan University Shanghai China Chair of Dependable Nano Computing Karlsruhe Institute of Technology Karlsruhe Germany

ISBN: (数字)9781728110851

ISBN: (纸本)9781728158020

Soft error is a major reliability concern in advanced technology nodes. Although mitigating Soft Error Rate (SER) will inevitably sacrifice area and power, few studies paid attention to optimization methods to explore trade-offs between area, power and SER. This paper proposes an optimization framework based on Bayesian approach for soft-error-tolerant circuit design. It comprises two steps:1) data preprocessing and 2) Bayesian optimization. In the preprocessing step, a strategy incorporating k-means algorithm and a novel sequencing algorithm is used to cluster Flip-Flops (FFs) with similar SER in order to reduce the dimensionality for the subsequent step. Bayesian Neural Network (BNN) is the applied surrogate model for acquiring the posterior distribution of three design metrics, while the Lower confidence bound (LCB) functions are employed as acquisition functions to select the next point based on BNN when optimizing. Finally, the non-dominated sorting genetic algorithm (NSGA-II) is used to search the Pareto Optimal Front (POF) solutions of three LCB functions. Experimental results demonstrate the proposed framework has a 1.4x improvement in accuracy and a 70% reduction in SER with acceptable increases in power and area.

关键词： Optical fibers Sequential analysis Neural networks Clustering algorithms Pareto optimization Bayes methods Circuit synthesis

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A Low Power 1.0 GHz VCO in 65nm-CMOS LP-Process

A Low Power 1.0 GHz VCO in 65nm-CMOS LP-Process

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2011 IEEE 9th International Conference on asic(2011年第九届IEEE国际专用集成电路大会)

作者： Zhang Zhang Xiaoyang Zeng Xu Cheng Zhiyi Yu Electronics and Apply Physical School Hefei University of Technology Hefei 230009 Anhui China State Key Lab of ASIC & System Fudan University Shanghai 201203 China

A l.0GHz, Voltage Controlled Oscillator (VCO) fabricated in TSMC 1.2V 1P9M 65nm CMOS LP-Process is presented in the paper. The output frequency is proportional to the control voltage (Vctrl). The advantage of the architecture is very simple and easy to be realized and it aims at low power, low area and low cost. Measured results show that the VCO operates at 400 MHz to 1.6 GHz while Vctrl ranges from 0.8V to 1.4V and the tuning range is even larger than 100％. The VCO works well in Register File and consumes 0.5 mA from a 1.2-V power supply, and occupies an area of 400 μm2.

关键词： Voltage-controlled oscillators Clocks Latches CMOS integrated circuits

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Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification 21

Late Breaking Results: Heterogeneous Circuit Layout Centerli...

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Proceedings of the 58th Annual ACM/IEEE Design Automation Conference

作者： Xiqiong Bai Ziran Zhu Peng Zou Lichong Sun Jianli Chen Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China National ASIC System Engineering Center School of Electronic Science and Engineering Southeast University Nanjing China State Key Lab of ASIC & System Fudan University Shanghai China HiSilicon Technologies CO. Ltd Shanghai China Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China and State Key Lab of ASIC & System Fudan University Shanghai China

ISBN: (纸本)9781665432740

With the continued feature-size shrinking in modern circuit designs, the layout performance estimation and parasitic import calculation based on the extracted centerline result play an important role in mask verification. Most previous works on layout centerline extraction focus on identifying the connectivity among the devices in a mask layout, with few ones collecting accurate centerline information for mask verification while considering design constraints. In this paper, we first formulate the centerline extraction problem as a Voronoi diagram to collect centerline points. Then, we present a graph-based invalid centerline removal algorithm to generate an initial centerline result. Finally, a complexity-driven centerline optimization method is proposed to further optimize the centerline while considering design constraints. Compared with the commercial 3D-RC parasitic parameter extraction tool RCExplorer and the 1st place in the 2019 EDA Elite Challenge Contest, experimental results show that our algorithm achieves the highest average precision ratio of 99.8% on centerline extraction while satisfying all design constraints in the shortest runtime.

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An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM

An Efficient Memory Partitioning Approach for Multi-Pattern ...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Binbin Liu Fan Yang Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A.

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

This paper presents an efficient memory partitioning algorithm for multi-pattern data access in Spintransfer torque random access memory (STT-RAM). The algorithm generates check patterns to solve read disturbance problem while ensuring multi-pattern data access in parallel. The implementation results imply that our proposed approach highly outperforms state-of-the-art algorithm in terms of bank number, searching time, performance and storage overhead.

关键词： Partitioning algorithms Arrays Memory management Random access memory Schedules Field programmable gate arrays Torque

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RLCkt: An Analog Circuit Automatic Sizing Sage Based on Reinforcement Learning

RLCkt: An Analog Circuit Automatic Sizing Sage Based on Rein...

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China Semiconductor Technology International Conference (CSTIC)

作者： Wangge Zuo Lingge Liu Fei Li Yifei Huang Liqian Zhang Jing Wan School of Information Science and Engineering State key lab of ASIC and System Fudan University Shanghai China Suzhou Foohu Technology Co. Ltd. Shanghai China

Automated solutions for sizing analog circuits have gained significant interest due to the labor-intensive nature of the task in a typical design cycle, especially with technology development and circuit scaling. This study introduces the RLCkt, an Analog Circuit Automatic Sizing Sage, which utilizes reinforcement learning (RL) and the SPICE simulator to automatically adjusts design parameters to meet performance metrics. After several hours of training, RLCkt runs 94 times faster than a traditional generic algorithm with comparable performance. Additionally, its generalization capability surpasses that of state-of-the-art methods.

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Design of a Novel One Transistor-Dram Based on Bulk Silicon Substrate

Design of a Novel One Transistor-Dram Based on Bulk Silicon ...

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China Semiconductor Technology International Conference (CSTIC)

作者： K. Xiao J. Liu Wei Wu Zheng Xu J. Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China Fujian Electronics & Information (Group) Co. LTD Fujian China

ISBN: (数字)9781728165585

ISBN: (纸本)9781728165592

In this work, we propose a novel device based on bulk silicon substrate and use it as a dynamic random access memory (DRAM) with TCAD simulation. The operation principle of this device is similar to that of Z 2 -FET which was demonstrated previously in SOI substrate. In our device, LDD doping and gate control are combined to build up the carrier injection barriers which enable feedback mechanism. The designed device shows similar sharp switch and gate-controlled hysteresis in its output characteristics. It is further demonstrated for DRAM application without need of extra capacitor. The DRAM operation shows high speed and reasonably long retention time.

关键词： Capacitors Random access memory Doping Logic gates Silicon Substrates Hysteresis

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Enhancement of endurance for CuxO based RRAM cell

Enhancement of endurance for CuxO based RRAM cell

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International Conference on Solid-state and Integrated Circuit Technology

作者： M. Yin P. Zhou H. B. Lv T. A. Tang B.A. Chen Y.Y. Lin A. Bao M. H. Chi School of Microelectronics and State Key Lab of ASIC & System Fudan University Shanghai China Memory Technology Development Center Semiconductor Manufacturing International Corp. Shanghai China

For the first time, we report that the copper oxide (Cu x O) based resistive random access memory (RRAM) cell can achieve 10 4 cycles (i.e. ~10x better) as a new record as well as elimination of the initial ¿forming¿ than reported in literature. The copper oxide is integrated in MIM (metal-insulator-metal) structure and is grown by plasma oxidation of Cu substrate, with CuO near upper surface and graded Cu x O (i.e. increasingly Cu rich or O-vacancies rich) toward the Cu substrate. A thinner CuO upper layer can eliminate ¿forming¿ process and, for in turn, greatly enhance the endurance of resistive switching by eliminating the damage during the ¿forming¿ process.

关键词： Copper Oxidation Plasma applications Substrates Electrodes Deformable models Random access memory Scanning electron microscopy Chemical analysis Spectroscopy

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Improvement of Endurance and Switching Stability of Forming-Free CuxO RRAM

Improvement of Endurance and Switching Stability of Forming-...

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IEEE International Memory Workshop (IMW)

作者： H. B. Lv M. Yin P. Zhou T. A. Tang B. A. Chen Y. Y. Lin A. Bao M. H. Chi School of Microelectronics and State Key Lab of ASIC & System Fudan University Shanghai China Memory Technology Development Center Semiconductor Manufacturing International Corp. Shanghai China

Cu-oxide grown by plasma oxidation is found typically composed of upper CuO layer and inner graded Cu x O. The initial forming process leads to endurance degradation but can be improved by annealing in an oxygen deficient ambient. By using ramped pulse and verification algorithm, the endurance and programming voltage shift are further ameliorated.

关键词： Stability Oxidation Degradation Random access memory CMOS process Plasma measurements Breakdown voltage Microelectronics Application specific integrated circuits Semiconductor device manufacture

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研究（英文） 2020年第2期 277-286页

作者： Shuiyuan Wang Xiang Hou Lan Liu Jingyu Li Yuwei Shan Shiwei Wu David Wei Zhang Peng Zhou ASIC & System State Key Lab. School of Microelectronics Fudan University Shanghai 200433 China Department of Physics State Key Laboratory of Surface Physics Key Laboratory of Micro and Nano Photonic Structures (Ministry of Education) and Institute for Nanoelectronic Devices and Quantum Computing Fudan University Shanghai 200433 China

The von Neumann bottleneck has spawned the rapid expansion of neuromorphic engineering and brain-like *** serve as bridges for information transmission and connection in the biological nervous *** direct implementation of neural networks may depend on novel materials and devices that mimic natural neuronal and synaptic *** exploiting the interfacial effects between MoS2 and AlOx,we demonstrate that an h-BN-encapsulated MoS2 artificial synapse transistor can mimic the basic synaptic behaviors,including EPSC,PPF,LTP,and *** optoelectronic spikes enable simulation of synaptic gain,frequency,and weight *** Pavlov classical conditioning experiment was successfully simulated by electrical tuning,showing associated learning *** addition,h-BN encapsulation effectively improves the environmental time stability of our *** h-BN-encapsulated MoS2 artificial synapse provides a new paradigm for hardware implementation of neuromorphic engineering.

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Efficient Model-Based OPC via Graph Neural Network

Efficient Model-Based OPC via Graph Neural Network

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Electronics Design Automation (ISEDA), International Symposium of

作者： Shuyuan Sun Xuelian Chen Fan Yang Bei Yu Shang Li Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University China Cogenda Inc China Department of Computer Science and Engineering The Chinese University of Hong Kong China

As feature size continues to shrink and light source wavelengths remain unchanged, the optical diffraction effects seriously degrade chip yield. Optical proximity correction (OPC) has become an essential step for chip manufacturability. However, OPC cannot achieve satisfactory mask correction results in an affordable number of iterations on some layouts, delaying the chip design cycle. In this paper, we propose to use the Graph Neural Network (GNN) to predict the initial mask correction and speed up model-based OPC. We design a graph model to represent the chip layout, with segments represented as graph nodes and the diffraction effects between them represented as graph edges. The GNN is used to obtain the embedding of the segment, and we predict the shift value based on its output. The proposed GNN-based predictor enhances the original OPC to find a good correction solution for full-chip-size masks in fewer iterations. compared with the original OPC method, experimental results on 55nm and 32nm full chip designs show that the proposed GNN-based OPC method reduces the number of iterations up to 75% and the acquired mask of comparable quality.

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