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International Conference on Ultimate Integration of Silicon, ULIS

作者： J. Liu X.Y. Cao A. Zaslavsky S. Cristoloveanu J. Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China Brown University Providence USA IMEP-LAHC INP-Grenoble/Minatec Grenoble France

ISBN: (数字)9781728116587

ISBN: (纸本)9781728116594

In this work, we demonstrate experimentally a novel photodiode built in the silicon-on-insulator (SOI) substrate. Compared to conventional photodiode, where the p-n junction is formed by diffusion or ion implantation, the p-n junction in our work is formed by electrostatic doping induced by top and bottom gates. The fabricated device used for photodetection at λ = 520 nm, shows a dark current 3 decades lower than a conventional photodiode. Furthermore, the device can be switched between photodiode mode with low reverse current and resistor mode with much higher current. This unique property can be exploited in the operation of a photodetector array.

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Electrical properties of metamorphic in0.52Al 0.48As/In0.65Ga0.35As HEMT's on GaAs substrate

Electrical properties of metamorphic in0.52Al 0.48As/In0.65G...

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ICSICT-2006: 2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Qiu, Z.J. Liu, R. Zhang, S.L. Gui, Y.S. Cui, L.J. Zeng, Y.P. Chu, J.H. School of Microelectronics Fudan University Shanghai 200433 China State Key Lab. of ASIC System and Micro/Nanoelectronics Science and Technology Innovation Platform Fudan University Shanghai 200433 China National Laboratory for Infrared Physics Shanghai Institute of Technical Physics Chinese Academy of Sciences Shanghai 200083 China Institute of Semiconductors Chinese Academy of Sciences Beijing 10008 China

ISBN: (纸本)1424401615

Variable magnetic field Hall measurements were performed to investigate the electrical properties in In0.52Al0.48As/In 0.65Ga0.35As metamorphic high electron mobility transistors (MMHEMT's) on GaAs substrate at the temperature range from 4 to 100 K. The Shubnikov-de Hass (SdH) measurement shows the two-dimensional electronic behavior and two-subband electron occupation in MMHEMT's. The electron densities and mobilities of the two subbands are obtained by fast Fourier transform analysis. Both the SdH oscillations and conventional Hall analysis are in good agreement in the determination of total electron density, which is about 2.1×1012 cm-2 due to incomplete transfer of the electrons. The temperature dependence of the electron mobility indicates that at low temperature alloy scattering dominates, whereas at high temperature, the mobility is mainly limited by optical phonon scattering. © 2006 IEEE.

关键词： High electron mobility transistors

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Learning Low-Rank Structured Sparsity in Recurrent Neural Networks

Learning Low-Rank Structured Sparsity in Recurrent Neural Ne...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Weijing Wen Fan Yang Yangfeng Su Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University China School of Mathematical Sciences Fudan University China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

Acceleration and wide deployability in deeper recurrent neural network is hindered by high demand for computation and memory storage on devices with memory and latency constraints. In this work, we propose a novel regularization method to learn hardware-friendly sparse structures for deep recurrent neural networks. Considering the consistency of dimension in continuous time units in recurrent neural networks, low-rank structured sparse approximations of the weight matrices are learned through the regularization without dimension distortion. Our method is architecture agnostic and can learn compact models with higher degree of sparsity than the state-of-the-art structured sparsity learning method. The structured sparsity rather than random sparsity also facilitates the hardware implementation. Experiments on language modeling of Penn TreeBank dataset show that our approach can reduce the parameters of stacked recurrent neural network model by over 90% with less than 1% perplexity loss. It is also successfully evaluated on larger highway neural network model with word2vec dataset like enwik8 and text8 using only 20M weights.

关键词： Recurrent neural networks Computer architecture Sparse representation Road transportation Hardware Logic gates

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A Novel PUF Using Stochastic Short-Term Memory Time of Oxide-Based RRAM for Embedded Applications

A Novel PUF Using Stochastic Short-Term Memory Time of Oxide...

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International Electron Devices Meeting (IEDM)

作者： Jianguo Yang Deyang Chen Qinting Ding Jinbei Fang Xiaoyong Xue Hangbing Lv Xiaoyang Zeng Ming Liu Zhejiang Lab Hangzhou China Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of the Chinese Academy of Sciences Beijing China State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9781728188881

ISBN: (纸本)9781728188898

RRAM suffers from poor retention with short-term memory time when using low compliance current for programing. However, the short-term memory time exhibits ideal randomness, which can be exploited as an entropy source for physically unclonable function (PUF). In this work, we demonstrated a novel PUF utilizing the stochastic short-term memory time of oxide-based RRAM. The proposed PUF was implemented on a 256Kb HfO 2 /WO x bilayer RRAM test chip in 0.13μm logic process. The RRAM PUF is capable of regenerating >10 20 times after 10 years@115°C and the bit error rate (BER) remains

关键词： Temperature measurement Microprocessors Stochastic processes Computer architecture Transforms Entropy Sensors

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New degradation mechanisms and reliability performance in tunneling field effect transistors

New degradation mechanisms and reliability performance in tu...

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International Electron Devices Meeting (IEDM)

作者： G. F. Jiao Z. X. Chen H. Y. Yu X. Y. Huang D. M. Huang N. Singh G. Q. Lo D.-L. Kwong Ming-Fu Li State Key Lab ASIC & System Department Microelectronics Fudan University Shanghai China Institute of Microelectronics Agency for Science Technology and Research Singapore School of EEE Nanyang Technological University Singapore Singapore

ISBN: (纸本)9781424456390;9781424456406

Tunneling n-FET reliability performance is studied for the first time by physical analysis and experimental measurements. (1) A new degradation mechanism by interface trap induced change of tunneling field and current I d is demonstrated. (2) Under PBTI or HC stress, there is a strong peak of vertical electric field E x at the gate/source overlapping region due to the P + doping of the source, inducing high interface trap degradation. These explain the large PBTI and HC degradation, very different from those observed in conventional n-MOSFETs.

关键词： Degradation Tunneling FETs Performance analysis Current measurement Electric variables measurement Stress measurement Time measurement Doping MOSFET circuits

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Silicide as diffusion source for dopant segregation in 70-nm MOSFETs with PtSi Schottky-barrier source/drain on ultrathin-body SOI

Silicide as diffusion source for dopant segregation in 70-nm...

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2008 9th International Conference on Ultimate Integration on Silicon (ULIS 2008)

作者： Z. J. Qiu Z. Zhang J. Lu R. Liu M. Ostling S. L. Zhang State Key Lab of ASIC & System Fudan University Shanghai China School of Information and Communication Technology Royal Institute of Technology Stockholm Sweden The Ångström Laboratory Uppsala University Uppsala Sweden

In this paper, dopant segregation (DS) method is adopted to enhance device performance of PtSi-based Schottky-barrier source/drain MOSFETs (SB-MOSFETs) fabricated on ultrathin silicon-on-insulator. The DS formation is realized by means of Silicide As Diffusion Source. Without DS treatment, the devices are typically p-type, but with a rather large electron branch at positive gate bias. Dopant segregation with As is found to turn the devices to well-performing n-MOSFETs, and DS with B to greatly enhance the hole conduction in the p-MOSFETs. A large threshold voltage (V{sub}t) shift is however observed in the p-MOSFET due to B lateral spread caused during the drive-in process for the DS formation. By reducing the drive-in temperature, this problem is partially addressed with a smaller V{sub}t shift and a much better control of short channel effect.

关键词： Schottky-barrier MOSFET Dopant segregation Threshold voltage SADS

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An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling

An Efficient Bayesian Optimization Approach for Analog Circu...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Biao He Shuhan Zhang Fan Yang Changhao Yan Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University Shanghai P. R. China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A.

ISBN: (数字)9783981926347

ISBN: (纸本)9781728144689

Bayesian optimization with Gaussian Process (GP) models has been proposed for analog synthesis since it is efficient for the optimizations of expensive black-box functions. However, the computational cost for training and prediction of Gaussian process models are O(N 3 ) and O(N 2 ), respectively, where N is the number of data points. The overhead of the Gaussian process modeling would not be negligible as N is relatively large. Recently, a Bayesian optimization approach using neural network has been proposed to address this problem. It reduces the computational cost of training and prediction of Gaussian process models to O(N) and O(1), respectively. However, reducing the infinite-dimensional kernel to finite-dimensional kernel using neural network mapping would weaken the characterization ability of Gaussian process. In this paper, we propose a novel Bayesian optimization approach using Sparse Pseudo-input Gaussian Process (SPGP). The idea is to use M

关键词： Optimization Gaussian processes Computational modeling Bayes methods Integrated circuit modeling Training Predictive models

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Nanoimprint of ordered ferro/piezoelectric P(VDF-TrFE) nanostructures

Nanoimprint of ordered ferro/piezoelectric P(VDF-TrFE) nanos...

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作者： Fang, Jiang-Rong Shen, Zhen-Kui Yang, Shen Lu, Qian Li, Jinxing Chen, Yi-Fang Liu, Ran State Key Lab of ASIC and System Department of Microelectronics Fudan University Shanghai 200433 China Department of Material Science Fudan University Shanghai 200433 China Rutherford Appleton Laboratory Chilton Didcot Oxfordshire OX11 0QX United Kingdom Micro and Nanotechnology Centre United Kingdom School of Microelectronics Fudan University 220 Handan Road Shanghai China

The next generation of portable computing and communication devices tremendously depend on the technologies that enable the rapid manipulation, caching and high-density non-volatile data storage. The recent development of organic electronics requires high-quality organic memory compatible with other devices, which will eventually lead to the realization of all organic electronic systems. The challenge of the organic electronics application is to find less degradative ways of fabricating ferroelectric polymer nanostructures. In this work, we applied the nanoimprint technique to fabricate ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] copolymer line and dot nanostructures and compared the ferroelectric properties and domain formation in these two nanostructures. © 2011 Elsevier B.V. All rights reserved.

关键词： Nanostructures

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An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis

An Efficient Asynchronous Batch Bayesian Optimization Approa...

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Design Automation Conference

作者： Shuhan Zhang Fan Yang Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University Shanghai P. R. China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A.

ISBN: (数字)9781728110851

ISBN: (纸本)9781728158020

In this paper, we propose EasyBO, an Efficient ASYn-chronous Batch Bayesian Optimization approach for analog circuit synthesis. In this proposed approach, instead of waiting for the slowest simulations in the batch to finish, we accelerate the optimization procedure by asynchronously issuing the next query points whenever there is an idle worker. We introduce a new acquisition function which can better explore the design space for asynchronous batch Bayesian optimization. A new strategy is proposed to better balance the exploration and exploitation and guarantee the diversity of the query points. And a penalization scheme is proposed to further avoid redundant queries during the asynchronous batch optimization. The efficiency of optimization can thus be further improved. Compared with the state-of-the-art batch Bayesian optimization algorithm, EasyBO achieves up to 7.35× speed-up without sacrificing the optimization results.

关键词： Optimization Bayes methods Analog circuits Mathematical model Computational modeling Space exploration Uncertainty

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Fast and Robust DCNN Based Lithography SEM Image Contour Extraction Models

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Journal of Microelectronic Manufacturing 2021年第1期4卷 16-22页

作者： Tao Zhou Xuelong Shi Chen Li Yan Yan Bowen Xu Shoumian Chen Yuhang Zhao Wenzhan Zhou Kan Zhou Xuan Zeng Shanghai Integrated Circuits R&D Center Co. Ltd.ShanghaiChina2012032 Shanghai Huali Microelectronics Corporation ShanghaiChina2013173 State Key Lab of ASIC&System School of MicroelectronicsFudan UniversityShanghaiChina201203

Scanning electron microscope(SEM)metrology is critical in semiconductor manufacturing for patterning process quality assessment and *** feature width and feature-feature space dimension measurements from critical dimension SEM(CDSEM)images,visual inspection of SEM image also offers rich information on the quality of ***,visual inspection alone leaves considerable room of ambiguity regarding patterning *** narrow the room of ambiguity and to obtain more statistically quantitative information on patterning quality,SEM-image contours are often extracted to serve such *** contours,important information such as critical dimension and resist sidewall angle at any location can be *** geometrical information can be used for optical proximity correction(OPC)model verification and lithography hotspot detection,*** contour extraction algorithms based on local information have insufficient capability in dealing with noisy and low contrast *** achieve reliable contours from noisy and low contrast images,information beyond local should be made use of as much as *** this regard,deep convolutional neural network(DCNN)has proven its great capability,as manifested in various computer vision *** the full advantages of this maturing technology,we have designed a DCNN network and applied it to the task of extracting contours from noisy and low contrast SEM *** turns out that the model is capable of separating the resist top and bottom contours *** addition,the model does not generate false contours,it also can suppress the generation of broken contours when ambiguous area for contour extraction is small and *** advanced image alignment algorithm with sub-pixel accuracy,contours from different exposure fields of same process condition can be superposed to estimate process variation band,furthermore,stochastic effect induced edge placement variation statistics can eas

关键词： SEM images contour extraction machine leaning(ML) deep convolution neural network(DCNN) edge placement variation

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