A superpass-transistor (SPT) model is presented as a quantum-device candidate for future VLSI systems based on multiple-valued logic (MVL). A conceptual SPT structure based on the ideas of a lateral-resonant-tunnellin...
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A superpass-transistor (SPT) model is presented as a quantum-device candidate for future VLSI systems based on multiple-valued logic (MVL). A conceptual SPT structure based on the ideas of a lateral-resonant-tunnelling quantum-dot transistor (LQT) and a heterostructure FET is described. An important feature of the SPT is its capability of MVL signal detection and generation. A superpass gate (SP gate) corresponding to a single SPT is defined and is demonstrated to be a universal logic module for implementing highly compact multiple-valued VLSI systems. An algorithm suitable for synthesising minimal series-parallel SP-gate networks for MVL functions with many variables is proposed. The network allows both constants and variables as its pass inputs;accordingly, upsilon-subfunctions, where upsilon can be a constant or a variable, are defined. SP implicants, SP subimplicants and the consensus between SP subimplicants are also defined. The algorithm first generates all prime SP subimplicants from upsilon-subfunctions by using the consensus operation, then derives all prime SP implicants by using the implication operation, and finally selects an optimal set of prime SP implicants to cover the function by using existing methods.
The paper describes certain issues relevant to the development of a logic simulation engine, designed to be incorporated into a mixed-signal simulator. Usually, the rate-limiting process in any mixed-signal simulation...
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The paper describes certain issues relevant to the development of a logic simulation engine, designed to be incorporated into a mixed-signal simulator. Usually, the rate-limiting process in any mixed-signal simulation is the analogue processing but, for systems with a significant asymmetry between logic and analogue components, the efficiency of the logic engine can obviously become important. A technique is reported for improving both the space and time complexity of the logic engine: a method of event-queue searching using multiple cache pointers. Experimental results show that about five cache pointers provide the optimum efficiency gain from this technique. Finally, problems of event-queue management are reviewed, with particular reference to the situation where simulation time is represented by a real number, as it must be in a mixed-signal environment.
Instead of using the conventional m out of n perfect secret sharing scheme to protect a single secret among n users, the authors propose a secret sharing scheme based on one cryptographic assumption to protect multipl...
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Instead of using the conventional m out of n perfect secret sharing scheme to protect a single secret among n users, the authors propose a secret sharing scheme based on one cryptographic assumption to protect multiple secrets. It is shown that, with this relaxation of the security requirement, secret sharing and some related secret-sharing problems, such as cheater detection and secret broadcasting, can be solved very efficiently.
This paper introduces a simple O(NlogN) sequential algorithm that determines the admissibility of an arbitrary permutation to an N x N Multistage Cube-Type Network (MCTN) implemented by 2 X 2 switching elements (SEs) ...
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This paper introduces a simple O(NlogN) sequential algorithm that determines the admissibility of an arbitrary permutation to an N x N Multistage Cube-Type Network (MCTN) implemented by 2 X 2 switching elements (SEs) in contrast to previous O(Nlog(2)N) algorithms. It is proven that the new algorithm is optimal in the sense that any algorithm, based on bit-operations, has to examine at least (N/4)logN different bits among the total NlogN bits in the binary representations of the destinations numbered from 0 through N - 1.
Some performance simulation results of a remote-positioning system on a multitarget real-time context for oceanic instruments tracking are discussed and several indicators are considered to fine-tune the system's ...
We investigate a program behavior model that generates address reference strings including the interreference durations. This model views a trace as the sample path of a semi-Markov process. The transition probability...
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Electrical impedance tomography (EIT) is a non-invasive imaging technique which aims to image the impedance of material within a test volume from electrical measurements made on the surface. The reconstruction of impe...
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Electrical impedance tomography (EIT) is a non-invasive imaging technique which aims to image the impedance of material within a test volume from electrical measurements made on the surface. The reconstruction of impedance images is an ill-posed problem which is both extremely sensitive to noise and highly comput.tionally intensive. This paper defines an experimental measurement in EIT and calculates optimal experiments which maximize the distinguishability between the region to be imaged and a best estimate conductivity distribution. These optimal experiments can be derived from measurements made on the boundary. We describe a reconstruction algorithm, known as POMPUS, which is based on the use of optimal experiments. We have shown that, given some mild constraints, if POMPUS converges, it converges to a stationary point of our objective function. It is demonstrated to be many times faster than standard, Newton based, reconstruction algorithms. Results using synthetic data indicate that the images produced by POMPUS are comparable to those produced by these standard algorithms.
作者：
SHEN, XJComput. Sci. Telecommun. Program
Missouri Univ. Kansas City MO USA Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions
An N x N k-Omega network is obtained by adding k more stages in front of an Omega network An N-permutation defines a bijection between the set of N sources and the set of N destinations. Such a permutation is said to ...
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An N x N k-Omega network is obtained by adding k more stages in front of an Omega network An N-permutation defines a bijection between the set of N sources and the set of N destinations. Such a permutation is said to be admissible to a k-Omega if N conflict-free paths, one for each source-destination pair defined by the permutation, can be established simultaneously. When an N-permutation is not admissible, it is desirable to divide the N pairs into a minimum number of groups (passes) such that the conflict-free paths can be established for the pairs in each group. Raghavendra and Varma solved this problem for BPC (Bit Permutation Complement) permutations on an Omega without extra stage. This paper generalizes their result to a k-Omega where k can be any integer between 0 and n 1. An O(NIgN) algorithm is given which realizes any BPC permutation in a minimum number of passes on a k-Omega (0 less than or equal to k less than or equal to n 1).
In this paper, we analyze the performance of GI/GI/s/s+r systems. In particular we examine steady-state call blocking and time blocking. We vary several parameters such as the number of servers, the number of waiting ...
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