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3rd International Conference on Radiation Effects of electronic Devices, ICREED 2019

作者： Peng, Chao Lei, Zhifeng Zhang, Zhangang En, Yunfei Huang, Yun China Electronic Product Reliability and Environmental Testing Research Institute Science and Technology on Reliability Physics and Application of Electronic Component Laboratory Guangzhou510610 China

ISBN: (纸本)9781728173184

The neutron-induced secondary ions can cause single event effects through direct ionization, while the LET values of the secondary ions are quite lower than heavy ions in space. Monte Carlo simulation results show that although the maximum LET of secondary ions produced by different energy neutrons incident into the circuit can reach 25.6 MeV-cm2/mg, 98% of the secondary ions have LET values below 16 MeV-cm2/mg. This may lead to different charge collection mechanisms and single event transient (SET) characteristics for neutron. In this paper, the charge collection mechanisms of neutron secondary ions in a single 65 nm planar bulk transistor are studied through 3D TCAD simulations. The neutron-induced SET characteristics in planar bulk transistor, UTBB FDSOI and bulk/SOI FinFET are also compared. Based on the simulation results, UTBB FDSOI shows the best single event effect immunity compared with planar bulk transistor, bulk FinFET and SOI FinFET under the same technology node. © 2019 IEEE.

关键词： Neutrons

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Threshold Voltage Instability Mechanisms of SiC Power MOSFETs under Different Gate Preconditon Durations

Threshold Voltage Instability Mechanisms of SiC Power MOSFET...

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7th International Forum on Wide Bandgap Semiconductors&18th China International Forum on Solid State Lighting (第七届国际第三代半导体论坛暨第十八届中国国际半导体照明论坛)

作者： Yunliang Rao Yuan Chen Zhiyuan He Yiqiang Chen Xinbing Xu Yang Liu School of Electronics and Information Technology Sun Yat-sen University510006GuangzhouChina Scien Science and Technology on Reliability Physics and Application of Electronic Component Laboratory No. School of Electronics and Information Technology Sun Yat-sen University510006GuangzhouChina

在这项工作中，研究了不同栅极预偏置条件持续时间下SiC功率 MOSFETs的阈值电压不稳定性及其机理.这项工作中使用的SiC功率MOSFETs来自三个供应商，即某国产半导体公司、罗姆半导体和英飞凌，他们的产品分别地代表了具有平面栅极、双沟...

在这项工作中，研究了不同栅极预偏置条件持续时间下SiC功率 MOSFETs的阈值电压不稳定性及其机理.这项工作中使用的SiC功率MOSFETs来自三个供应商，即某国产半导体公司、罗姆半导体和英飞凌，他们的产品分别地代表了具有平面栅极、双沟槽栅极和非对称沟槽栅极的最先进的MOSFETs.

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Cryogenic Characterization of Nano-scale Bulk FinFETs 15

Cryogenic Characterization of Nano-scale Bulk FinFETs

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15th IEEE International Conference on Solid-State and Integrated Circuit technology, ICSICT 2020

作者： Fan, Lin-Jie Bi, Jin-Shun Fan, Xue Xu, Gao-Bo Xu, Yan-Nan Xi, Kai Zhang, Zhan-Gang Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China School of Electrical Engineering Chengdu Technological University Chengdu611730 China Science and Technology on Reliability Physics and Application of Electronic Component Laboratory China Electronic Product Reliability and Environmental Testing Research Institute Guangzhou510610 China

ISBN: (纸本)9781728162355

For the state-of-Art quantum technology applications, the effective control and high-speed reading of a large number of qubits require a combination of complementary metal-oxide-semiconductor (CMOS) circuits in cryogenic temperatures environments. In this letter, the electrical responses of bulk fin field effect transistor (FinFET) devices that could be applied in quantum controllers have been investigated under cryogenic conditions. The devices under test are high-k metal gate bulk FinFETs with 35 nm channel length. The electrical properties of the FinFET device are greatly optimized at cryogenic temperatures. As the temperature decreases, the FinFET exhibits a larger saturation current, smaller subthreshold swing, larger maximum transconductance, and smaller gate-induced drain leakage current. These results provide experimental evidence for the implementation of the FinFET in control systems for quantum chips in cryogenic environments. © 2020 IEEE.

关键词： Cryogenics

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An R-SIFT Image Matching Intelligent Algorithm Applied to Hardware Trojan Detection

An R-SIFT Image Matching Intelligent Algorithm Applied to Ha...

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作者： Chen Sun Pujiang Liang Lingling Li Jingjing Ma Licheng Jiao Fang Liu Science and Technology on Reliability Physics and Application of Electronic Component Laboratory Key Laboratory of Intelligent Perception and Image Understanding of Ministry of Education International Research Center for Intelligent Perception and ComputationJoint International Research Laboratory of Intelligent Perception and ComputationSchool of Artificial IntelligenceXidian University

Malicious modification, deletion or addition of some modules in the integrated circuits(ICs) will cause the chip to be attacked, which is called Hardware Trojans(HTs). Reverse engineering(RE) is a classic destructive method and widely used in HTs detection. However, RE is very time-consuming and error prone. In this paper, based on RE, we propose the R-SIFT algorithm to match image and reformulate the Trojan detection problem as change detection problem. For the R-SIFT algorithm, the ratio of exponentially weighted averages(Roewa) operator is introduced into the scale-invariant feature transform(SIFT) algorithm. Experiments show that the proposed method has 7 to 56 times more matching points than the original SIFT can be effectively applied to HTs detection.

关键词： Trojan detection R-SIFT Image matching

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Degradation Studies on 8-Layer 3D Vertical Resistive Random Access Memory Under Moisture

Degradation Studies on 8-Layer 3D Vertical Resistive Random ...

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International Symposium on Physical & Failure Analysis of Integrated Circuits

作者： Dengyun Lei Huiwei Wu Yiqiang Chen Yun Huang Yunfei En Qiantong Guo Feng Zhang Rui Gao Science and Technology on Reliability Physics and Application of Electronic Component Laboratory The No.5 Electronics Research Institute of the Ministry of Industry and Information Technology Guangzhou China China Electronics Corporation Beijing China Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China

Resistive random-access memory (RRAM) is a promising alternative to Flash memory. For high density application, 3D vertical RRAM (VRRAM) is a cost-effective method that attracts many attentions. However, the VRRAM also has some reliability issues. In this paper, the degradation under moisture stress is studied. High resistant state(HRS) is sensitive to moisture, while the low resistant state(LRS) remains stable. So, the moisture stress decreases the memory window. This degradation is caused by the moisture invasion HfO2/TaOx interface along the side wall and reduce the barrier of the interface. Based on Poole-Frenkel emission, this paper models the degradation mechanism to illustrate the process.

关键词： Degradation Resistance Integrated circuits Three-dimensional displays Resistive RAM Moisture Hafnium compounds

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A reliability evaluation software for Flip Chip based on failure physics

A reliability evaluation software for Flip Chip based on fai...

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International Conference on (ICEPT) electronic Packaging technology

作者： Si Chen Qiushi Wu Zhiwei Fu Yun Huang Bin Yao Bin Zhou Physics and Application of Electronic Component Laboratory Science and Technology on Reliability Guangzhou China School of Electronic and Information Engineering South China University of Technology Guangzhou China

ISBN: (数字)9781728168265

ISBN: (纸本)9781728168272

This paper introduces the flip chip reliability evaluation software developed based on failure physics. Firstly, the system framework of the software is introduced, and then the core algorithm of the software is described. Key parameters such as stress, strain, plastic strain energy density, displacement, acceleration can be extracted, and the service life of the selected structure is obtained through relevant failure physical models. The lifetime of each key structure is used to obtain the lifetime of the whole flip chip device through the competition algorithm of short board effect. An example of Flip chip device reliability evaluation under condition of standard GJB548B-2005 method 1010.1 C temperature cycling was given, it shows that the predicted device life is 207 cycles.

关键词： Load modeling Software Analytical models Software reliability Flip-chip devices Finite element analysis

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Black equation of the electromigration lifetime for ceramic package with lead bumps and plastic package with lead-free bump

Black equation of the electromigration lifetime for ceramic ...

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International Conference on (ICEPT) electronic Packaging technology

ISBN: (数字)9781728168265

ISBN: (纸本)9781728168272

In this study, electromigration accelerated life tests of lead-containing copper pillar bumps in ceramic packages and lead-free copper pillar bumps in plastic packages were carried out at different current densities and ambient temperatures. The electromigration life prediction model based on Black equation was established for the two. The influence index n and activation energy Q of current density of interconnection bumps with two structures were determined through MTTF analysis of samples. Based on the life prediction model, the effects of substrate material, temperature and current density parameters on electromigration life were compared. Finally, considering the influence of Joule heating effect and current crowding effect, the electromigration life prediction models of the two bumps are modified.

关键词： Copper Electromigration Lead Resistance Ceramics Mathematical model Plastics

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Performance Enhancement Mechanisms and Optimization of Multi-Pass Parallel Flow Condensers with Liquid-Vapor Separation

SSRN

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SSRN 2024年

作者： Pu, Jin Huan Hua, Nan Jian, Xiaodong Chen, Ying Li, Yongliang Yang, Tong Wang, Hua Sheng Shandong Institute for Advanced Technology Shandong University Shandong Jinan250061 China Ningbo Institute of Technology Beihang University Zhejiang Ningbo315832 China School of Engineering and Materials Science Queen Mary University of London LondonE1 4NS United Kingdom The Science and Technology on Reliability Physics Application of Electronic Component Laboratory The 5th Electronics Research Institute The Ministry of Industry and Information Technology Guangdong Guangzhou510610 China School of Material and Energy Guangdong University of Technology Guangdong Guangzhou510006 China School of Chemical Engineering University of Birmingham BirminghamB15 2TT United Kingdom Faculty of Science and Technology Middlesex University LondonNW4 4BT United Kingdom

This study employed a distributed-parameter model developed by the authors to investigate the mechanisms of condensation heat transfer enhancement using liquid-vapor separation (LS) in multi-pass parallel flow condensers (MPFCs). Additionally, tube pass arrangements for MPFCs with LS were optimized. Simulations characterized relationships among refrigerant flow rate, vapor quality, flow patterns, heat-transfer coefficient and pressure drop at tube level, along with heat-transfer coefficient and tube-wall temperature distributions at the segment level. An entropy analysis based on the second law of thermodynamics quantified contributions from heat transfer and pressure drop. The results demonstrate that introducing LS leads to (1) a 9.1% increase in the average heat-transfer coefficient, (2) a 50.4% reduction in pressure drop, (3) similar entropy generation numbers due to heat transfer for both MPFC and MPFC-LS, (4) significantly higher entropy generation numbers due to pressure drop in the last two tube passes, and (5) a 51.4% lower average entropy generation number for MPFC-LS compared to MPFC. Compared to a baseline serpentine condenser, MPFCs-LS reduced pressure drop by 84% to 98% while maintaining nearly the same heat transfer rate, resulting in an overall performance improvement of 5% to 9%. The optimal tube-pass arrangement for MPFCs-LS was identified as 3-3-2-2-2-2-2-1-1-1-1. © 2024, The Authors. All rights reserved.

关键词： Parallel flow

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Temperature Hysteresis Effect of Q-factor in Vacuum Packaged MEMS Device

Temperature Hysteresis Effect of Q-factor in Vacuum Packaged...

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International Conference on (ICEPT) electronic Packaging technology

作者： Xianshan Dong Qinwen Huang Ping Lai Shaohua Yang Wei Su Yun Huang Science and Technology on Reliability Physics and Application of Electronic Component Laboratory No.5 Electronics Research institute of the Ministry of Industry and Information Technology Guangzhou China

ISBN: (数字)9781728168265

ISBN: (纸本)9781728168272

Vacuum packaging technology is commonly used in MEMS device to improve performance. Yet, the temperature influence of vacuum packaging on the MEMS device is rarely studied. In this paper, temperature hysteresis effect of Q-factor in vacuum packaged MEMS device was studied. The experimental test was carried out, and the mechanism was also investigated. Four kinds of MEMS gyroscope with different pressure were designed, and their temperature characteristic of Q-factor were measured. The results show that the packaged pressure influences the temperature hysteresis of Q-factor greatly, and lower pressure packaging would cause larger temperature hysteresis of Q-factor. This study is helpful for designer to understand the influence of vacuum packaging and improve temperature performance for vacuum packaged MEMS device.

关键词： Temperature Q-factor Hysteresis Micromechanical devices Temperature measurement Packaging Gyroscopes

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Thermal-Electric-Mechanical coupling simulation of Cu Pillar Bumps under AC current

Thermal-Electric-Mechanical coupling simulation of Cu Pillar...

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International Conference on Numerical Electromagnetic Modeling and Optimization for RF, Microwave, and Terahertz applications (NEMO)

作者： Kai Li Zhiwei Fu Si Chen GuoYuan Li Jile Xu School of Micro-Electronics South China University of Technology Guangzhou China Science and Technology on Reliability Physics and Application of Electronic Component Laboratory Guangzhou China

ISBN: (数字)9781728169668

ISBN: (纸本)9781728169675

With the development of 3D IC, the electromigration of Cu pillar bumps under AC conditions is currently given wide attention. The thermal-electric-mechanical coupling simulation was realized by using the direct coupling element of ANSYS software. We find out that the maximum thermal gradient (TG) is located at IMC layer in the Cu pillar bumps. Due to the large CTE mismatch between the Cu trace and the Si chip, the maximum stress is occurred within the Cu trace. The maximum current density (JS) is located in the middle of the Cu trace and at the corner of the Cu pillar. In addition, during the loading of AC current, with the increase of loading time, the stress and temperature will both increase in the early stage of loading. However, with the current loading continues (t ≥ 0.625s), the temperature and stress gradually maintain at a stabilized level, but show significant fluctuation. With the increase of current frequency, the curves of fluctuation stage will be more and more smooth, and gradually fit to the curve of DC. It is also found that there is a lag between temperature/stress and AC current in the fluctuation stage.

关键词： Couplings Heating systems Fluctuations Loading Silicon Finite element analysis Stress

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