Vertical Gate All Around Nanowire Complementary FET based logic circuits offer an alternative way for higher cell density without aggressive gate length scaling. In this study, we develop a device to circuit design-te...
详细信息
ISBN:
(纸本)9798350362206;9798350362190
Vertical Gate All Around Nanowire Complementary FET based logic circuits offer an alternative way for higher cell density without aggressive gate length scaling. In this study, we develop a device to circuit design-technology co-optimization (DTCO) flow that incorporates Virtual Fab Semiconductor Process Modeling and physics-based TCAD simulations. We compare VGAA Complementary FET (CFET) based 6T SRAM with its counterparts by conventional planar CMOS, sequential / monolithic 3DIC CFETs with lateral transistors, accounting for the parasitics from virtual fab modeling. Our results show that VGAA CFETs offer better control over the channel and reduce parasitic capacitances and resistances compared to the counterpart technology options.
The PbS colloidal quantum dots (CQDs) have garnered significant attention in the realm of infrared photodetectors (PDs) owing to their advantageous features, such as monolithic integration with silicon-based readout c...
详细信息
In this paper, the circuit design of the all-GaN Two-stage Turn-off Over-Current Protection circuit (TT-OCP) is proposed. The TT-OCP can realize the over-current protection of GaN power HEMTs through a two-stage turn-...
详细信息
Widespread millimeter wave applications have promoted rapid development of system in package (SiP) and antenna in package (AiP). Most AiP structures take the form of flip chip onto antenna substrate, where signal inte...
详细信息
Widespread millimeter wave applications have promoted rapid development of system in package (SiP) and antenna in package (AiP). Most AiP structures take the form of flip chip onto antenna substrate, where signal interconnect losses are introduced by solder humps. The integration may be unavailable for chips with fine pad pitches. Fan-out wafer level package (FOWLP) with antenna patterning on redistributed layers (RDL) is another method for millimeter wave AiP. In this project, a hybrid integration AiP structure is developed. The microwave monolithicintegrated circuit (MMIC) chip and antenna unit are integrated with chip-first FOWLP process. Multilayer organic substrate with fine pitch RDL interconnections meets the requirements of wideband antenna design. Modified coplanar waveguide is adopted to feed 2 x 2 aperture array formed on RDL layer. Package warpage is measured using Shadow Moire techniques. The antenna forms an aperture-coupled stacked patch array with bandwidth 25% and gain 8.5dBi for 60 GHz digital communication system. The proposed approach is a convenient hybrid integration solution adopting FOWLP process for millimeter wave AiP systems.
This article presents an enhanced physical SPICE model for insulated gate bipolar transistor (IGBT) modules, grounded in a two-dimensional charge distribution. The model accurately delineates the lateral charge distri...
详细信息
This article presents an enhanced physical SPICE model for insulated gate bipolar transistor (IGBT) modules, grounded in a two-dimensional charge distribution. The model accurately delineates the lateral charge distribution under both static conduction and transient conditions, providing a precise representation of the PNP and PIN components of the IGBT. The improved model more effectively describes current distribution and clarifies parasitic effects, such as latch-up phenomenon. Furthermore, a negative carrier lifetime near the gate is introduced in accordance with the carrier movement direction, resulting in a catenary charge distribution in the PIN segment of the IGBT. This aligns closely with the technology computer-aided design (TCAD) results. Notably, the carrier concentration in the N(-)base region significantly escalates under high-level injection conditions. The model incorporates an N+N- junction and a P+N- junction within the channel to portray the carrier concentration variation during the transient state, also factoring in the effect of temperature on the IGBT characteristics. Implemented in PSPICE, the model's findings are compared with TCAD outcomes and experimental data. These comparisons illustrate that the proposed model precisely delivers the charge distribution, as well as dynamic/static characteristics and unbalanced current in parallel devices of the IGBT.
The exponential growth of data exerts great pressure on hardware design for database systems. Memory-centric computing (MCC) architecture, which enable compute capabilities near or inside memory storage, demonstrate g...
详细信息
ISBN:
(数字)9798350350579
ISBN:
(纸本)9798350350586
The exponential growth of data exerts great pressure on hardware design for database systems. Memory-centric computing (MCC) architecture, which enable compute capabilities near or inside memory storage, demonstrate great potential in enhancing the efficiency of database operations with higher compute parallelism and reduced data movements. However, existing MCC architecture mainly focus on artificial intelligence (AI) computations and those designed for database applications can only run a limited number of standalone queries such as SORT or JOIN, lacking efficient support for increasingly diverse and complex database workloads. For example, realizing a commercial recommendation engine on database requires supporting workloads including but not limited to vector aggregation, convolution or
$N$
-hop neighborhoods computing, etc. In this work, we develop a memristor-enabled memory-centric instruction-set architecture (MeMCISA) aiming to efficiently accelerate versatile workloads in modern database systems. MeMCISA features scalable multi-bank memristor-based storage organization with near-memory circuitries and caches in banks. An out-of-order (O0O) scheduling scheme is designed for MeMCISA based on a vector instruction set with four types of instructions (bit-level, element-level, vector-level, and control-level), combining memristor-enabled in-memory computing and near-memory computing to efficiently run workloads with varying computational kernels and data sizes. MeMCISA can support parallel instruction executions across different memristor banks as well as different hardware modules within a memristor bank. Furthermore, we develop data dependency handling mechanisms to support vector dependency scenarios in MeMCISA that do not exist in conventional scalar-based instruction sets. A prototype MeMCISA is implemented based on a 40nm CMOS technology with necessary peripheral hardware including instruction buffer and instruction scheduler. To accurately study MeMCI
The emerging Au-assisted exfoliation technique provides a wealth of large-area and high-quality ultrathin two-dimensional (2D) materials compared with traditional tape-based exfoliation. Fast, damage-free, and reliabl...
详细信息
This work focuses on the significant demand for breakthroughs and improvements in chip performance through the monolithic heterogeneous integration of GaN-based materials and devices with foreign substrates in the pos...
详细信息
ISBN:
(数字)9798331519919
ISBN:
(纸本)9798331519926
This work focuses on the significant demand for breakthroughs and improvements in chip performance through the monolithic heterogeneous integration of GaN-based materials and devices with foreign substrates in the post-Moore era. It systematically conducts the fabrication of wafer-scale single-crystal GaN film and its heterogeneous integration by ion-cutting technology.
Interfacial fatigue degradation and crack formation of wire bonds are one of the serious issues related to packaging in power modules that affect the reliability of power electronics. This work presents a new approach...
详细信息
Interfacial fatigue degradation and crack formation of wire bonds are one of the serious issues related to packaging in power modules that affect the reliability of power electronics. This work presents a new approach based on a combination of phase field modeling and finite element analysis to study the electro-thermo-mechanical behavior, the interface degradation and crack propagation processes of wire bonded interconnects in insulated-gate bipolar transistor (IGBT) power modules. The strain energy density obtained from the macroscale electro-thermo-mechanical analysis is transferred to the meso-scale phase field modeling to study the interface fatigue and crack propagation, considering the effect of wire grain morphology. The temperature and stress distribution characteristics of a typical IGBT power module with Al wire bonds under power cycling are investigated. Stress concentration at the interconnect interface caused by thermal strains between wire and chip is examined. The crack length increases with increasing cycle number. The presence of Al grain boundaries is found to have a significant impact on crack propagation, due to grain boundary energy and weakening effects. The developed model could provide new insights for predicting the lifetime and crack growth of power modules, and offer a pathway for the reliability optimization of wire bonds.
We have compared the memory performance of vertical structure InGaZnO (IGZO) channel ferroelectric field effect transistors (FETs) with channel-all-around and gate-all-around structures by 3D TCAD simulation for high-...
详细信息
ISBN:
(数字)9798350361834
ISBN:
(纸本)9798350361841
We have compared the memory performance of vertical structure InGaZnO (IGZO) channel ferroelectric field effect transistors (FETs) with channel-all-around and gate-all-around structures by 3D TCAD simulation for high-density application. The memory window (MW), on current (Ion), and subthreshold swing (SS) are systematically studied and discussed in terms of ferroelectric film thickness, channel thickness, and diameter. It reveals that the channel-all-around structure has a larger MW and higher Ion due to the overlap region between the gate and drain/source based on this simulation, while the memory performance of the gate-all-around structure can be improved through shrinking the length of the underlap region.
暂无评论