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检索条件"机构=Science and Technology on Parallel & Distributed Processing Laboratory"

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Program Optimization of Stencil Based Application on the GPU-Accelerated System

Program Optimization of Stencil Based Application on the GPU...

引用

International Symposium on parallel and distributed processing with Applications, ISPA

作者： Guibin Wang Xuejun Yang Ying Zhang Tao Tang XuDong Fang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

Graphic processing Unit (GPU), with many light-weight data-parallel cores, can provide substantial parallel computational power to accelerate general purpose applications. But the powerful computing capacity could not be fully utilized for memory-intensive applications, which are limited by off-chip memory bandwidth and latency. Stencil computation has abundant parallelism and low computational intensity which make it a useful architectural evaluation benchmark. In this paper, we propose some memory optimizations for a stencil based application mgrid from SPEC 2 K benchmarks. Through exploiting data locality in 3-level memory hierarchies and tuning the thread granularity, we reduce the pressure on the off-chip memory bandwidth. To hide the long off-chip memory access latency, we further prefetch data during computation through double-buffer. In order to fully exploit the CPU-GPU heterogeneous system, we redistribute the computation between these two computing resource. Through all these optimizations, we gain 24.2 x speedup compared to the simple mapping version, and get as high as 34.3 x speedup when compared with a CPU implementation.

关键词： Concurrent computing Application software Acceleration Yarn Delay distributed processing distributed computing Bandwidth parallel processing Prefetching

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SEMCS: A Precise Memory-Hierarchy Simulation Framework on parallel Full-System Simulator

SEMCS: A Precise Memory-Hierarchy Simulation Framework on Pa...

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WASE International Conference on Information Engineering, ICIE

作者： Junjie Wu Xiaohui Pan Guanghui Liu Xuejun Yang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

The memory wall problem makes researches on memory hierarchy more and more important. And in these researches, software simulation plays a significant role. To model the real runtime environment, full system simulators have been widely used. However, researchers are often perplexed by the precise problem when they run a parallel program on a full system multi-core simulator, especially in multiple configurations. Because the influence arising from operating system and the relative execution speed of parallel threads often make the performance of target programs uncertain. To solve the precise problem, this paper proposes a single execution multi-configuration simulation framework (SEMCS). Then we design and implement a Simics module, called trans-multicast using the SEMCS framework. Finally, we test a benchmark from SPEComp2001 on a four core processor in three memory hierarchy configurations. And the result has verified the effectiveness of the SEMCS framework.

关键词： Computational modeling Operating systems Testing Read-write memory Computer simulation Concurrent computing Yarn Cache memory Laboratories distributed processing

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SCQR - A P2P Query Routing Algorithm Based on Semantic Cluster

SCQR - A P2P Query Routing Algorithm Based on Semantic Clust...

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International Symposium on Intelligent Ubiquitous Computing and Education

作者： Shiyao Jin Gui-Ming Zhu School of Computer Science National University of Defense Technology Changsha China National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

The low efficiency and uncertainty routing is correct is a problem for resource location of an unstructured p2p network. It is hard to achieve high query hit with small cost and low latency for such kind of network. In this paper, we present a p2p query routing algorithm which is based on semantic cluster (SCQR). SCQR makes nodes clustered according to their semantic, and each cluster elects a super-node as cluster computing node which is responsible for computing cluster semantic and establishing links with all neighbor cluster computing nodes. Query is routed among cluster computing nodes. SCQR achieves high query hit with small routing latency and query cost in both analytical theoretical and experimental studies.

关键词： Query processing Clustering algorithms Peer to peer computing Routing Delay Costs Computer networks Frequency Floods Intelligent networks

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An Optimal Mapping Algorithm Based on Balanced Load Cutting for DVE Systems

An Optimal Mapping Algorithm Based on Balanced Load Cutting ...

引用

International Symposium on Intelligent Information technology Application, IITA

作者： Wei Zhang Min Xi Hangjun Zhou Yuxing Peng Sikun Li National Laboratory for Parallel and Distributed Processing National University of Defense Technology ChangSha China Department of Computer Science Xi'an Jiaotong University Xi'an China

In distributed virtual environment (DVE) systems, a distributed server infrastructure is often used to reduce the latency between servers and clients. Under this infrastructure, mapping clients to proper servers is one of the key issues for improving the interactivity and overall performance. Most traditional methods of mapping the clients to servers only consider the load balancing problem. However, there are two other important aspects that should be involved: the physical world integrity and the virtual world integrity. In this work, we propose a novel mapping algorithm which takes care of all three aspects at the same time. The algorithm converts the mapping problem into cutting stage and matching stage to get optimal result with polynomial complexity. The experimental results show that our algorithm improves the overall performance of DVE systems significantly.

关键词： Delay Network servers Computer science Virtual environment Load management Polynomials Quality of service Information technology Application software distributed processing

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An incremental learning algorithm for supervised neural network with contour preserving classification

An incremental learning algorithm for supervised neural netw...

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International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information technology, ECTI-CON

作者： Piyabute Fuangkhon Thitipong Tanprasert Parallel and Distributed Computing Research Laboratory Faculty of Science and Technology Assumption University Bangkok Thailand

This paper presents an alternative algorithm for integrating the existing knowledge of a supervised learning neural network with the new training data. The algorithm allows the existing knowledge to age out in slow rate as a neural network is gradually retrained with consecutive sets of new samples, resembling the change of application locality under a consistent environment. The algorithm also utilizes the contour preserving classification algorithm to increase the accuracy of classification. The experiment is performed on 2-dimension partition problem and the result convincingly confirms the effectiveness of the algorithm.

关键词： Neural networks Support vector machines Support vector machine classification Supervised learning Partitioning algorithms Neurons Classification algorithms Speech recognition Data mining distributed computing

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Feedback-Based Energy-aware Scheduling Algorithm for Hard Real-time Tasks

Feedback-Based Energy-aware Scheduling Algorithm for Hard Re...

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International Conference on Networking, Architecture, and Storage (NAS)

作者： Dong-song Zhang Shi-yao Jin Tong Wu Hua-wei Li National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China Zhenjiang Watercraft College Jiangsu China

In this paper, we propose a new algorithm for dynamic voltage scaling (DVS) based on feedback control mechanism. Besides handling a periodic tasks, our algorithm significantly reduces the energy consumption of periodic tasks and consequently the energy consumption of the whole task set. The results show that, comparing to on-line dynamic voltage scaling (the best algorithm to our knowledge), our approach improves the energy savings by 10% on most task sets tested and by 5% on average.

关键词： Scheduling algorithm Dynamic voltage scaling Feedback control Processor scheduling Real time systems Energy consumption Voltage control Switches Heuristic algorithms Dynamic scheduling

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Optimizing Reference Gene Set for Inter-Chip Normalization Using Genetic Algorithm

Optimizing Reference Gene Set for Inter-Chip Normalization U...

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International Conference on BioMedical Engineering and Informatics (BMEI)

作者： Fei Li Wenjian Xu Peng Li XiaoChen Bo Yuxing Peng Department of Computer Science National Laboratory of Parallel & Distributed Processing National University of Defense Technology Changsha China Beijing Institute of Radiation Medicine Beijing China

Due to the existence of systematic bias in the measurements, inter-chip normalization is required before integrated data analysis of multiple microarray datasets. Current inter-chip normalization methods rely on some assumptions, which can rarely be verified by experiments, such as the invariant expression level of housekeeping genes or the stability of statistical data distribution. In this paper, we present a highly verifiable inter-chip normalization method using genetic optimization algorithm, which depends only on a small number of housekeeping genes, and therefore facilitates experimental validation without any accuracy lost.

关键词： Genetic algorithms Gene expression Laboratories Data analysis Optimization methods Genomics Bioinformatics Statistical distributions Probes Computer science

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Model-Directed Multi-Level parallelization for Multi-Task Programs on the Cell BE

Model-Directed Multi-Level Parallelization for Multi-Task Pr...

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International Symposium on Computer science and its Applications, CSA

作者： Miao Wang Nicolas Benoit Francois Bodin National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China University of Rennes I Rennes France

ISBN: (纸本)9781424449453;9781424449460

Multi-core architectures can deliver high processing power if the multiple levels of parallelism they expose are exploited. However, it is non-trivial to orchestrate the computational and memory resources allocation. Furthermore, when dealing with distributed memory architectures, data distribution adds another level of complexity. This paper presents a model-driven technique for mapping multi-task parallel programs onto multi-core platforms. The resource allocation configurations are expressed within a three-dimensional optimization space which affects task-level and data-level parallelism, and communication. Then, the performance of any valid parallelization scheme is estimated statically, taking into account both computation and communication costs. We prototyped our approach on the Cell BE with an image processing application. Experiments show that our model can correctly predict the overall performance and highlight the most efficient parallelization schemes.

关键词： parallel processing Resource management Concurrent computing Multicore processing Image processing Predictive models Embedded computing Space exploration Laboratories distributed processing

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An Irregular cutting based distributed mapping algorithm for DVE systems

An Irregular cutting based distributed mapping algorithm for...

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Pacific-Asia Workshop on Computational Intelligence and Industrial Application, PACIIA

作者： Wei Zhang Hangjun Zhou Yuxing Peng Sikun Li Min Xi National Laboratory of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha China Department of Computer Science Xi'an Jiaotong University Xi'an China

distributed Virtual Environment (DVE) systems have become more and more important both in academic communities and the industries. To guarantee the load constrain, the physical world integrity and the virtual world integrity, the virtual environment should be divided into several parts and mapped to multiple servers, which are located in geographically different places. Many centralized algorithms based on regular cutting method are proposed to solve this problem. However, the dynamic property of clients and distributed property of the system make the existing algorithms unable to undertake it. In this paper, we propose a metric to measure the cutting quality and design a distributed mapping algorithm based on an irregular cutting. Simulation results show that our algorithm greatly decreases the costs of DVE systems for migration of clients and effectively improves the satisfaction degree of users.

关键词： Defense industry Virtual environment Computer industry Computer science Algorithm design and analysis Delay Partitioning algorithms Industrial training Computational intelligence Application software

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Numerical study of DIBL effect in Carbon Nanotube-FETs

Numerical study of DIBL effect in Carbon Nanotube-FETs

引用

IEEE Conference on Nanotechnology

作者： Hailiang Zhou Bingcai Sui Yaqing Chi Minxuan Zhang Yue Hao National laboratory of parallel and distributed processing National University of Defense Technology Changsha China Department of Microelectronics Xidian University Xi'an China

ISBN: (纸本)9781424448326

In CNFETs, the Drain Induced Barrier Lowing (DIBL) effect is still a primitive problem and open for further study. Based on a numerical model developed with the Non-Equilibrium Green's Function (NEGF) approach in real space, this paper studied the DIBL effect in Carbon Nanotube-FETs (CNFETs). Some interesting phenomena of the impact of DIBL on the energy band have been noticed. For example, the relationship between the degree of barrier lowing and the drain-source voltage is not linear but of a step-like quantization, and the energy band shape (gradient or aclinic) is closely related to Fermi-level. For the first time, a detailed explanation of the underlying physical mechanism of the observed DIBL effect is presented according to the electronic structure, the effective capacitance model and the quantum capacitance model of CNFETs. Then the correlation between DIBL effect and the insulator thickness, insulator dielectric constant, CNT diameter and channel length is studied. At the end, a conclusion is made by summarizing the differences between the DIBL effect in CNFETs and that in short channel MOSFETs, and several approaches is presented to reduce the leakage current resulting from the DIBL effect.

关键词： Carbon nanotubes Quantum capacitance Dielectrics and electrical insulation Numerical models Green's function methods Voltage Quantization Shape Dielectric constant MOSFETs

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