The Embarrassingly parallel(EP) algorithm which is typical of many Monte Carloapplications provides an estimate of the upper achievable limits for double precision performance of parallel supercomputers. Recently, Int...
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The Embarrassingly parallel(EP) algorithm which is typical of many Monte Carloapplications provides an estimate of the upper achievable limits for double precision performance of parallel supercomputers. Recently, Intel released Many Integrated Core(MIC) architecture as a many-core co-processor. MIC often offers more than 50 cores each of which can run four hardware threads as well as 512-bit vector instructions. In this paper,we describe how the EP algorithm is accelerated effectively on the platforms containing MIC using the offload execution model. The result shows that the efficientimplementation of EP algorithm on MIC can take full advantage of MIC's computational resources and achieves a speedup of 3.06 compared with that on Intel Xeon E5-2670 CPU. Based on the EP algorithm on MIC and an effective task distribution model, the implementation of EP algorithm on a CPU-MIC heterogeneous platform achieves the performance of up to2134.86 Mop/s and 4.04 times speedup compared with that on Intel Xeon E5-2670 CPU.
With the development of high performance computing and Web 2.0 applications,unstructured data storage becomes more and more *** RDBMS isn't efficient for big data ***,RDBMS's scalability is ***' expansion ...
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With the development of high performance computing and Web 2.0 applications,unstructured data storage becomes more and more *** RDBMS isn't efficient for big data ***,RDBMS's scalability is ***' expansion often leads to a large scale of data *** paper designs and implements a high performance distributed key-value database,which is distributed Stage *** servers are organized by a consistent hashing ring and distributed with the support of Zookeeper,a distributed service *** has a high single-node read/write *** route information is calculated by clients,which reduces the expense of expansion.
Cloud services must upgrade continuously in order to maintain ***,a large body of empirical evidence suggests that,upgrade procedures used in practice are failure-prone and often cause planned or unplanned *** this pa...
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Cloud services must upgrade continuously in order to maintain ***,a large body of empirical evidence suggests that,upgrade procedures used in practice are failure-prone and often cause planned or unplanned *** this paper,we first define what is cloud service online upgrade,and then we analyze the shortcomings of current mainstream cloud service online upgrade *** particular,the mixed version problem along with rolling upgrade and the capacity loss problem brought by split mode upgrade have been *** that,we propose a solution called Delayed Switch,which can conduct cloud service upgrade with lower loss of availability and capacity in contrast with existing *** prove the performance of delayed switch in theory and develop a prototype system applying this *** by conducting experiments with a typical e-commerce service named Rubis,we validate the effectiveness and efficiency of our approach.
Resource allocation for multi-user across multiple data centers is an important problem in cloud computing environments. Many geographically-distributed users may request virtualized resources simultaneously. And the ...
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The double-precision matrix-matrix multiplication (DGEMM) on ARMv8 64-bit multi-core processor architecture was realized and optimized, and the optimal model for the purpose of maximizing the compute-to-memory access ...
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The contribution of parasitic bipolar amplification to SETs is experimentally verified using two P-hit target chains in the normal layout and in the special layout. For PMOSs in the normal layout, the single-event cha...
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The contribution of parasitic bipolar amplification to SETs is experimentally verified using two P-hit target chains in the normal layout and in the special layout. For PMOSs in the normal layout, the single-event charge collection is composed of diffusion, drift, and the parasitic bipolar effect, while for PMOSs in the special layout, the parasitic bipolar junction transistor cannot turn on. Heavy ion experimental results show that PMOSs without parasitic bipolar amplification have a 21.4% decrease in the average SET pulse width and roughly a 40.2% reduction in the SET cross-section.
The basic algorithm of HPL was introduced. Two optimization methods of communication, i.e., advanced-lookahead and dynamic broadcasting algorithm, were proposed. The performances of the two optimization methods were e...
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In the paper, a new implementation of a 3GPP LTE standards compliant turbo decoder based on GPGPU is proposed. It uses the newest GPU-Tesla K20c, which is based on the Kepler GK110 architecture. The new architecture h...
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ISBN:
(纸本)9781479944156
In the paper, a new implementation of a 3GPP LTE standards compliant turbo decoder based on GPGPU is proposed. It uses the newest GPU-Tesla K20c, which is based on the Kepler GK110 architecture. The new architecture has more powerful parallel computing capability and we use it to fully exploit the parallelism in the turbo decoding algorithm in novel ways. Meanwhile, we use various memory hierarchies to meet various kinds of data demands on speed and capacity. Simulation shows that our implementation is practical and it gets 76% improvement on throughput over the latest GPU implementation. The result demonstrates that the newest Kepler architecture is suitable for turbo decoding and it can be a promising reconfigurable platform for the communication system.
Fingerprint matching is a key procedure in fingerprint identification applications. The fingerprint-matching algorithm based on minutiae is one of the most typical algorithms that can achieve a reasonably correct reco...
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Fingerprint matching is a key procedure in fingerprint identification applications. The fingerprint-matching algorithm based on minutiae is one of the most typical algorithms that can achieve a reasonably correct recognition rate. Performance and cost are two critical factors when implementing minutia-based matching algorithms in most embedded applications. A low-cost, fully pipelined architecture for minutia-based fingerprint matching is proposed in this paper. A regular matching unit with a pipeline of 13 stages is designed as the core of the architecture, interfacing with a two-port RAM and a DDR3 controller. We implemented the whole architecture on a Xilinx FPGA board with the Virtex VII XC7VX485T chip. The matching unit can run with a frequency of 330 MHz on the chip, which leads the system to achieve a throughput of about 430000 fingerprints per second when processing typical datasets. The unit only occupies 568 slices, which is less than 1% of the available chip resources. The board only consumes 16 W of power when run. The architecture can gain about twice the throughput of the 2.93 GHz Intel Xeon5670 CPU at a low logic cost and power.
The Embarrassingly parallel (EP) algorithm which is typical of many Monte Carlo applications provides an estimate of the upper achievable limits for double precision performance of parallel supercomputers. Recently, I...
详细信息
ISBN:
(纸本)9781479920327
The Embarrassingly parallel (EP) algorithm which is typical of many Monte Carlo applications provides an estimate of the upper achievable limits for double precision performance of parallel supercomputers. Recently, Intel released Many Integrated Core (MIC) architecture as a many-core co-processor. MIC often offers more than 50 cores each of which can run four hardware threads as well as 512-bit vector instructions. In this paper, we describe how the EP algorithm is accelerated effectively on the platforms containing MIC using the offload execution model. The result shows that the efficient implementation of EP algorithm on MIC can take full advantage of MIC's computational resources and achieves a speedup of 3.06 compared with that on Intel Xeon E5-2670 CPU. Based on the EP algorithm on MIC and an effective task distribution model, the implementation of EP algorithm on a CPU-MIC heterogeneous platform achieves the performance of up to 2134.86 Mop/s and 4.04 times speedup compared with that on Intel Xeon E5-2670 CPU.
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