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arXiv 2022年

作者： Yin, Shangfei Wang, Qinglin Hao, Ruochen Zhou, Tianyang Mei, Songzhu Liu, Jie Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha410073 China College of Computer National University of Defense Technology Changsha410073 China

General Matrix Multiplication (GEMM) has a wide range of applications in scientific simulation and artificial intelligence. Although traditional libraries can achieve high performance on large regular-shaped GEMMs, they often behave not well on irregular-shaped GEMMs, which are often found in new algorithms and applications of high-performance computing (HPC). Due to energy efficiency constraints, low-power multi-core digital signal processors (DSPs) have become an alternative architecture in HPC systems. Targeting multi-core DSPs in FTm7032, a prototype CPU-DSPs heterogeneous processor for HPC, an efficient implementation - ftIMM - for three types of irregular-shaped GEMMs is proposed. FtIMM supports automatic generation of assembly micro-kernels, two parallelization strategies, and auto-tuning of block sizes and parallelization strategies. The experiments show that ftIMM can get better performance than the traditional GEMM implementations on multi-core DSPs in FT-m7032, yielding on up to 7.2× performance improvement, when performing on irregular-shaped GEMMs. And ftIMM on multi-core DSPs can also far outperform the open source library on multi-core CPUs in FT-m7032, delivering up to 3.1× higher efficiency. Copyright © 2022, The Authors. All rights reserved.

关键词： Digital signal processors

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AUXILIARY-TASKS LEARNING FOR PHYSICS-INFORMED NEURAL NETWORK-BASED PARTIAL DIFFERENTIAL EQUATIONS SOLVING

arXiv

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arXiv 2023年

作者： Yan, Junjun Chen, Xinhai Wang, Zhichao Zhou, Enqiang Liu, Jie Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha410073 China Laboratory of Digitizing Software for Frontier Equipment National University of Defense Technology Changsha410073 China

Physics-informed neural networks (PINNs) have emerged as promising surrogate modes for solving partial differential equations (PDEs). Their effectiveness lies in the ability to capture solution-related features through neural networks. However, original PINNs often suffer from bottlenecks, such as low accuracy and non-convergence, limiting their applicability in complex physical contexts. To alleviate these issues, we proposed auxiliary-task learning-based physics-informed neural networks (ATL-PINNs), which provide four different auxiliary-task learning modes and investigate their performance compared with original PINNs. We also employ the gradient cosine similarity algorithm to integrate auxiliary problem loss with the primary problem loss in ATL-PINNs, which aims to enhance the effectiveness of the auxiliary-task learning modes. To the best of our knowledge, this is the first study to introduce auxiliary-task learning modes in the context of physics-informed learning. We conduct experiments on three PDE problems across different fields and scenarios. Our findings demonstrate that the proposed auxiliary-task learning modes can significantly improve solution accuracy, achieving a maximum performance boost of 96.62% (averaging 28.23%) compared to the original single-task PINNs. The code and dataset are open source at https://***/junjun-yan/ATL-PINN. Copyright © 2023, The Authors. All rights reserved.

关键词： Partial differential equations

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Modeling Full Information with Graph Network for Joint Entity-Relation Extraction

Modeling Full Information with Graph Network for Joint Entit...

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2021年第四届算法、计算和人工智能国际会议

作者： Qian Wan Luona Wei Xinhai Chen Jie Liu Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology College of Systems Engineering National University of Defense Technology Laboratory of Software Engineering for Complex Systems National University of Defense Technology

Fully capturing contextual information and analyzing the association between entity semantics and type is helpful for joint extraction task: 1) The context can reflect the part of speech and semantics of entity. 2) The entity type is closely related to the relation between entities. Previous research used to simply embed the contextual information into shallow layer of the model, ignoring the association between entity semantics and type. In this paper, we propose a graph network with full-information modeling to explicitly model different-level information in the text. The contextual information of entity is dynamically embedded in each span representation to improve the reasoning ability. To capture the fine-grained association between the semantics and type of entity, the graph network uses the feature of entity types to generate edge information between different nodes. Experimental results show that our model outperforms previous models on the Co NLL04 dataset and obtains competitive results on the SciERC dataset in both entity recognition and relation extraction. Extensive additional experiments further verify the effectiveness of the model.

关键词： Named Entity Recognition Relation Extraction Natural Language Processing Graph Network Deep Learning

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A Novel Run-time Load Balancing Method for MapReduce

A Novel Run-time Load Balancing Method for MapReduce

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International Conference on Computer science and Network technology

作者： Zhihong Liu Yaping Liu Baosheng Wang Zhenghu Gong College of Computer National University of Defense Technology Changsha Hunan China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781467381741

In recent years, many companies are embracing the Hadoop MapReduce system for large-data processing with completion time constrains. However, exiting Hadoop schedulers still suffer from the reducer load imbalancing problem. In this paper, we present a novel run-time load balancing method for MapReduce. Our approach predicts the workload of each reduce task at run-time, and assigns the reduce tasks to specified machines based on the estimated workload of reduce tasks dynamically. Therefore, our approach can achieve load balance among machines. The experimental results show that our approach achieves high accuracy while predicting the workload of reduce tasks, and improves the job completion time by up to 23.15%.

关键词： MapReduce load balancing task scheduling Load balancing TASK SCHEDULING Completion time Runtime Workload Religious Missions

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Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs

Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Ve...

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IEEE Computer Society Annual Symposium on VLSI

作者： Sheng Liu Hanyan Chen Jianghua Wan Yaohua Wang College of Computer National University of Defense Technology Changsha Hunan China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781467390408

Binary Exchange Algorithm (BEA) always introduces excessive shuffle operations when mapping FFTs on vector SIMD DSPs. This can greatly restrict the overall performance. We propose a novel mod (2P-1) shuffle function and Mod-BEA algorithm (MBEA), which can halve the shuffle operation count and unify the shuffle mode. Such unified shuffle mode inspires us to propose a set of novel mod (2P-1) shuffle memory-access instructions, which can totally eliminate the shuffle operations. Experimental results show that the combination of MBEA and the proposed instructions can bring 17.2%-31.4% performance improvements at reasonable hardware cost, and compress the code size by about 30%.

关键词： Digital signal processing Hardware Pipelines Computer architecture Linearity Computers Software

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A Simulated Annealing Technique for Optimizing Time Warp Simulation

A Simulated Annealing Technique for Optimizing Time Warp Sim...

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International Conference on Computer Modeling and Simulation, ICCMS

作者： Wei Zhang Sina Meraji Jun Wang Carl Tropper National Laboratory of Parallel and Distributed Processing School of Computer Science National University of Defense Technology ChangSha China School of Computer Science McGill University Montreal Canada

According to Moore's law the complexity of VLSI circuits has doubled approximately every two years, resulting in simulation becoming the major bottleneck in the circuit design process. parallel and distributed simulations can be applied as fast, cost effective approaches to the simulation of large, complex circuits. In this paper, a simple yet effective simulated annealing-based approach is proposed to optimize the choice of a time window for optimistic parallel simulation. We chose gate level circuits simulations as our experimental vehicle. Our results show up to a 52% improvement in the simulation time using our simulated annealing algorithm. To the best of our knowledge, this is the first time that SA has been applied to optimize the performance of time warp simulations.

关键词： Time warp simulation Simulated annealing Circuit simulation Computational modeling Hardware design languages Discrete event simulation Computer simulation Voltage control Concurrent computing Computer science

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Improving unsupervised domain adaptation by reducing bi-level feature redundancy

arXiv

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arXiv 2020年

作者： Wang, Mengzhu Zhang, Xiang Lan, Long Wang, Wei Tan, Huibin Luo, Zhigang Science and Technology on Parallel and Distributed Laboratory College of Computer National University of Defense Technology Changsha China Institute for Quantum State Key Laboratory of High Performance Computing National University of Defense Technology Changsha China DUT-RU International School of Information Science & Engineering Dalian University of Technology DalianLiaoning116000 China Department of Science and Technology on Parallel and Distributed Processing National University of Defense Technology Changsha China

Reducing feature redundancy has shown beneficial effects for improving the accuracy of deep learning models, thus it is also indispensable for the models of unsupervised domain adaptation (UDA). Nevertheless, most recent efforts in the field of UDA ignore this point. Moreover, main schemes realizing this in general independent of UDA purely involve a single domain, thus might not be effective for cross-domain tasks. In this paper, we emphasize the significance of reducing feature redundancy for improving UDA in a bi-level way. For the first level, we try to ensure compact domain-specific features with a transferable decorrelated normalization module, which preserves specific domain information whilst easing the side effect of feature redundancy on the sequel domain-invariance. In the second level, domain-invariant feature redundancy caused by domain-shared representation is further mitigated via an alternative brand orthogonality for better generalization. These two novel aspects can be easily plugged into any BN-based backbone neural networks. Specifically, simply applying them to ResNet50 has achieved competitive performance to the state-of-the-arts on five popular benchmarks. Our code will be available at https://***/dreamkily/gUDA. © 2020, CC BY.

关键词： Deep learning

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Enhancing the Security of parallel Programs via Reducing Scheduling Space

Enhancing the Security of Parallel Programs via Reducing Sch...

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IEEE International Symposium on Dependable, Autonomic and Secure Computing (DASC)

作者： Xu Zhou Gen Li Kai Lu Shuangxi Wang School of Computer National University of Defense Technology Changsha PR China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha PR China

parallel programs face a new security problem - concurrency vulnerability, which is caused by a special thread scheduling instead of inputs. In this paper, we propose to automatically fix concurrency vulnerabilities by reducing thread scheduling space. Our method is based on two observations. First, most concurrency vulnerabilities are caused by atomicity violation errors. Second, reducing thread scheduling space does not harm the correctness of the original program. We designed a prototype runtime system shield using deterministic multithreading techniques. Shield is designed to transparently run parallel programs and schedule threads in large instruction blocks to prevent atomicity violation at best effort. In case some concurrency vulnerabilities cannot be fixed by shield's scheduling reducing scheme, we also provide a remedy strategy by integrating shield with record&replay function, so that it can help programmers to analyze attacker's behavior for manually fixing.

关键词： Concurrent computing Instruction sets Scheduling Runtime Computer bugs Security Processor scheduling

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Routing with uncertainty in wireless mesh networks

Routing with uncertainty in wireless mesh networks

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International Workshop on Quality of Service

作者： Fajun Chen Jiangchuan Liu Zongpeng Li Yijie Wang Key Laboratory of Science and Technology for National Defence of Parallel and Distributed Processing National University of Defense Technology China School of Computing Science Simon Fraser University Department of Computer Science University of Caglary

Existing routing protocols for Wireless Mesh Networks (WMNs) are generally optimized with statistical link measures, while not addressing on the intrinsic uncertainty of wireless links. We show evidence that, with the transient link uncertainties at PHY and MAC layers, a pseudo-deterministic routing protocol that relies on average or historic statistics can hardly explore the full potentials of a multi-hop wireless mesh. We study optimal WMN routing using probing-based online anypath forwarding, with explicit consideration of transient link uncertainties. We show the underlying connection between WMN routing and the classic Canadian Traveller Problem (CTP). Inspired by a stochastic recoverable version of CTP (SRCTP), we develop a practical SRCTP-based online routing algorithm under link uncertainties. We study how dynamic next hop selection can be done with low cost, and derive a systematic selection order for minimizing transmission delay. We conduct simulation studies to verify the effectiveness of the SRCTP algorithms under diverse network configurations. In particular, compared to deterministic routing, reduction of end-to-end delay (51.15~73.02%) and improvement on packet delivery ratio (99.76%) are observed.

关键词： Uncertainty Wireless mesh networks Delay Routing protocols Physical layer Statistics Stochastic processes Relays Computer networks Concurrent computing

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A Fast Adversarial Sample Detection Approach for Industrial Internet-of-Things Applications

A Fast Adversarial Sample Detection Approach for Industrial ...

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International Workshop on Quality of Service

作者： Shigeng Zhang Yudong Li Shuxin Chen Xuan Li Jian Zhang School of Computer Science and Engineering Central South University College of Computer Science and Electronic Engineering Hunan University The Science and Technology on Parallel and Distributed Processing Laboratory (PDL) China

Adversarial attacks reveal the inherent vulnerability of deep neural networks, which face serious security issues for their security. Among them, the attack against the Deep Neural Network (DNN) application used in the Industrial Internet of Things (IIoT) is a key area in adversarial attacks. Adversarial examples generated by attackers by adding human-undetectable interference to legitimate examples may cause models to make wrong decision results, resulting in serious accidents. Many detection technologies have been proposed to mitigate the harm of adversarial examples to neural networks, among which the methods based on the difference of feature attribution between normal examples and adversarial examples show state-of-the-art detection performance, but they suffer from detection efficiency. In this work, we focus on improving the detection efficiency of the feature-attribution-based detection methods. We observe that there is still a significant difference in the feature attribution distribution of a normal image and an adversarial image even only some pixels in the image are processed, which can be verified by utilizing the Kolmogorov-Smirnov test. Based on this observation, we first adopt a variety of strategies to sample partial pixels in an image and then utilize the selected pixels to train a feature-attribution-based detector for detecting adversarial examples. Extensive experiments conducted on four datasets (MNIST, CIFAR-10, SVHN, CIFAR-100) against various attacks proved that the detection efficiency of the accelerated detection method is improved (for example, the average execution time was increased by 8.7 times on CIFAR-10) while the detection performance maintains state-of-the-art.

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