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作者： Lu, Kai Zhou, Xu Bergan, Tom Wang, Xiaoping Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China College of Computer National University of Defense Technology Changsha China University of Washington Computer Science and Engineering United States

Multithreaded programs execute nondeterministically on conventional architectures and operating systems. This complicates many tasks, including debugging and testing. Deterministic multithreading (DMT) makes the output of a multithreaded program depend on its inputs only, which can totally solve the above problem. However, current DMT implementations suffer from a common inefficiency: they use frequent global barriers to enforce a deterministic ordering on memory accesses. In this paper, we eliminate that inefficiency using an execution model we call deterministic lazy release consistency (DLRC). Our execution model uses the Kendo algorithm to enforce a deterministic ordering on synchronization, and it uses a deterministic version of the lazy release consistency memory model to propagate memory updates across threads. Our approach guarantees that programs execute deterministically even when they contain data races. We implemented a DMT system based on these ideas (RFDet) and evaluated it using 16 parallel applications. Our implementation targets C/C++ programs that use POSIX threads. Results show that RFDet gains nearly 2x speedup compared with DThreads-a start-of-the-art DMT system. © 2014 ACM.

关键词： C++ (programming language)

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Efficient deterministic multithreading without global barriers 14

Efficient deterministic multithreading without global barrie...

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Proceedings of the 19th ACM SIGPLAN symposium on Principles and practice of parallel programming

ISBN: (纸本)9781450326568

Multithreaded programs execute nondeterministically on conventional architectures and operating systems. This complicates many tasks, including debugging and testing. Deterministic multithreading (DMT) makes the output of a multithreaded program depend on its inputs only, which can totally solve the above problem. However, current DMT implementations suffer from a common inefficiency: they use frequent global barriers to enforce a deterministic ordering on memory accesses. In this paper, we eliminate that inefficiency using an execution model we call deterministic lazy release consistency (DLRC). Our execution model uses the Kendo algorithm to enforce a deterministic ordering on synchronization, and it uses a deterministic version of the lazy release consistency memory model to propagate memory updates across threads. Our approach guarantees that programs execute deterministically even when they contain data races. We implemented a DMT system based on these ideas (RFDet) and evaluated it using 17 parallel applications. Our implementation targets C/C++ programs that use POSIX threads. Results show that RFDet gains nearly 2x speedup compared with DThreads-a start-of-the-art DMT system. Copyright © 2014 ACM.

关键词： C++ (programming language)

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MTracer: A Trace-Oriented Monitoring Framework for Medium-Scale Distributed Systems

MTracer: A Trace-Oriented Monitoring Framework for Medium-Sc...

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2014 IEEE 8th International Symposium on Service Oriented System Engineering

作者： Jingwen Zhou Zhenbang Chen Haibo Mi Ji Wang Science and Technology on Parallel and Distributed Processing Laboratory Changsha China

Trace-oriented runtime monitoring is a very effective method to improve the reliability of distributed systems. However, for medium-scale distributed systems, existing trace-oriented monitoring frameworks are either not powerful or efficient enough, or too complex and expensive to deploy and maintain. In this paper, we present MTracer, which is a lightweight trace-oriented monitoring system for medium-scale distributed systems. We have proposed and implemented several optimizations to improve the efficiency of the monitor server in MTracer. A web-based frontend is also provided to visualize a monitored system from different perspectives. We have validated MTracer in a real medium-scale environment. The results indicate that MTracer has a very lower overhead, and can handle more than 4000 events per second.

关键词： Monitoring Servers Optimization Databases Runtime Data mining Reliability

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Accelerating Embarrassingly parallel Algorithm on Intel MIC

Accelerating Embarrassingly Parallel Algorithm on Intel MIC

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2014 IEEE International Conference on Progress in Informatics and Computing

作者： Qinglin Wang Jie Liu XiantuoTang Feng Wang Guitao Fu Zuocheng Xing Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology

The Embarrassingly parallel(EP) algorithm which is typical of many Monte Carloapplications provides an estimate of the upper achievable limits for double precision performance of parallel supercomputers. Recently, Intel released Many Integrated Core(MIC) architecture as a many-core co-processor. MIC often offers more than 50 cores each of which can run four hardware threads as well as 512-bit vector instructions. In this paper,we describe how the EP algorithm is accelerated effectively on the platforms containing MIC using the offload execution model. The result shows that the efficientimplementation of EP algorithm on MIC can take full advantage of MIC's computational resources and achieves a speedup of 3.06 compared with that on Intel Xeon E5-2670 CPU. Based on the EP algorithm on MIC and an effective task distribution model, the implementation of EP algorithm on a CPU-MIC heterogeneous platform achieves the performance of up to2134.86 Mop/s and 4.04 times speedup compared with that on Intel Xeon E5-2670 CPU.

关键词： NPB embarrassingly parallel algorithm heterogeneous platform many integrated core architecture

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Design and Implementation of Distributed Stage DB:A High Performance Distributed Key-Value Database

Design and Implementation of Distributed Stage DB:A High Per...

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2014 International Conference on Industrial Engineering and Information technology

作者： Hui-jun Wu Kai Lu Gen Li Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology

With the development of high performance computing and Web 2.0 applications,unstructured data storage becomes more and more *** RDBMS isn't efficient for big data ***,RDBMS's scalability is ***' expansion often leads to a large scale of data *** paper designs and implements a high performance distributed key-value database,which is Distributed Stage *** servers are organized by a consistent hashing ring and distributed with the support of Zookeeper,a distributed service *** has a high single-node read/write *** route information is calculated by clients,which reduces the expense of expansion.

关键词： Distributed system,database,key-value,Zookeeper

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Location-Aware Multi-user Resource Allocation in Distributed Clouds

Location-Aware Multi-user Resource Allocation in Distributed...

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10th Annual Conference of Advanced Computer Architecture, ACA 2014

作者： Li, Jiaxin Li, Dongsheng Zheng, Jing Quan, Yong National Key Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China Information Center of Logistics Department Beijing China School of Computer Science National University of Defense Technology Changsha China

ISBN: (纸本)9783662444900

Resource allocation for multi-user across multiple data centers is an important problem in cloud computing environments. Many geographically-distributed users may request virtualized resources simultaneously. And the distances from users to allocated resources have much impact on the quality of service (QoS) in multiple data centers environment. Most existing methods do not take all these factors into account when allocating resources. They usually result in poor runtime performance of users' virtual computing environment and the remarkable difference of users' QoS. In this paper, we propose RAMD, a resource allocation algorithm based on multi-stage decision in multiple data centers. The RAMD algorithm allocate VMs to users, taking into account the correlation and interaction between multiple users, so as to minimize the sum of all users' service distances (i.e. determined by user location and network distance of virtual machines). Experimental results show that the algorithm can effectively deal with the cloud resource allocation for multi-user across multiple data centers. It can improve the runtime performance of users' virtualized resources and reduce the difference of QoS. © Springer-Verlag Berlin Heidelberg 2014.

关键词： Resource allocation

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The acceleration of turbo decoder on the newest GPGPU of Kepler architecture

The acceleration of turbo decoder on the newest GPGPU of Kep...

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International Symposium on Communications and Information Technologies (ISCIT)

作者： Yang Zhang Zuocheng Xing Luechao Yuan Cang Liu Qinglin Wang Science and technology on Parallel and distributed processing laboratory National University of Defense Technology ChangSha China

ISBN: (纸本)9781479944156

In the paper, a new implementation of a 3GPP LTE standards compliant turbo decoder based on GPGPU is proposed. It uses the newest GPU-Tesla K20c, which is based on the Kepler GK110 architecture. The new architecture has more powerful parallel computing capability and we use it to fully exploit the parallelism in the turbo decoding algorithm in novel ways. Meanwhile, we use various memory hierarchies to meet various kinds of data demands on speed and capacity. Simulation shows that our implementation is practical and it gets 76% improvement on throughput over the latest GPU implementation. The result demonstrates that the newest Kepler architecture is suitable for turbo decoding and it can be a promising reconfigurable platform for the communication system.

关键词： Decoding Graphics processing units parallel processing Computer architecture Throughput Kernel Bit error rate

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Experimental verification of the parasitic bipolar amplification effect in PMOS single event transients

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Chinese Physics B 2014年第7期23卷 775-779页

作者： He Yi-Bai Chen Shu-Ming College of Computer National University of Defense Technology Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology

The contribution of parasitic bipolar amplification to SETs is experimentally verified using two P-hit target chains in the normal layout and in the special layout. For PMOSs in the normal layout, the single-event charge collection is composed of diffusion, drift, and the parasitic bipolar effect, while for PMOSs in the special layout, the parasitic bipolar junction transistor cannot turn on. Heavy ion experimental results show that PMOSs without parasitic bipolar amplification have a 21.4% decrease in the average SET pulse width and roughly a 40.2% reduction in the SET cross-section.

关键词：重离子实验放大效应单事件双极寄生 PMOS 验证瞬态

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A low-cost fully pipelined architecture for fingerprint matching

A low-cost fully pipelined architecture for fingerprint matc...

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International Conference on Signal processing Proceedings (ICSP)

作者： Jinwei Xu Jingfei Jiang Yong Dou Xiaolong Shen Science and Technology on Parallel and distributed Processing Laboratory National University of Defense Technology Changsha China

Fingerprint matching is a key procedure in fingerprint identification applications. The fingerprint-matching algorithm based on minutiae is one of the most typical algorithms that can achieve a reasonably correct recognition rate. Performance and cost are two critical factors when implementing minutia-based matching algorithms in most embedded applications. A low-cost, fully pipelined architecture for minutia-based fingerprint matching is proposed in this paper. A regular matching unit with a pipeline of 13 stages is designed as the core of the architecture, interfacing with a two-port RAM and a DDR3 controller. We implemented the whole architecture on a Xilinx FPGA board with the Virtex VII XC7VX485T chip. The matching unit can run with a frequency of 330 MHz on the chip, which leads the system to achieve a throughput of about 430000 fingerprints per second when processing typical datasets. The unit only occupies 568 slices, which is less than 1% of the available chip resources. The board only consumes 16 W of power when run. The architecture can gain about twice the throughput of the 2.93 GHz Intel Xeon5670 CPU at a low logic cost and power.

关键词： Fingerprint recognition Throughput Random access memory Pipelines Computer architecture Field programmable gate arrays Algorithm design and analysis

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Accelerating embarrassingly parallel algorithm on Intel MIC

Accelerating embarrassingly parallel algorithm on Intel MIC

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IEEE International Conference on Progress in Informatics and Computing (PIC)

作者： Qinglin Wang Jie Liu Xiantuo Tang Feng Wang Guitao Fu Zuocheng Xing Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

ISBN: (纸本)9781479920327

The Embarrassingly parallel (EP) algorithm which is typical of many Monte Carlo applications provides an estimate of the upper achievable limits for double precision performance of parallel supercomputers. Recently, Intel released Many Integrated Core (MIC) architecture as a many-core co-processor. MIC often offers more than 50 cores each of which can run four hardware threads as well as 512-bit vector instructions. In this paper, we describe how the EP algorithm is accelerated effectively on the platforms containing MIC using the offload execution model. The result shows that the efficient implementation of EP algorithm on MIC can take full advantage of MIC's computational resources and achieves a speedup of 3.06 compared with that on Intel Xeon E5-2670 CPU. Based on the EP algorithm on MIC and an effective task distribution model, the implementation of EP algorithm on a CPU-MIC heterogeneous platform achieves the performance of up to 2134.86 Mop/s and 4.04 times speedup compared with that on Intel Xeon E5-2670 CPU.

关键词： Microwave integrated circuits Computer architecture Vectors Algorithm design and analysis Graphics processing units Clustering algorithms Load modeling

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