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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Guiming Wu Yong Dou Gregory D. Peterson National Laboratory for Parallel & Distributed Processing National University of Defense Technology Changsha China Electrical Engineering and Computer Science University of Tennessee Knoxville TN USA

To efficiently perform large matrix LU decomposition on FPGAs with limited local memory, the original algorithm needs to be blocked. In this paper, we propose a block LU decomposition algorithm for FPGAs, which is applicable for matrices of arbitrary size. We introduce a high performance hardware design, which mainly consists of a linear array of processing elements (PEs), to implement our block LU decomposition algorithm. A total of 36 PEs can be integrated into a Xilinx Virtex-5 xc5vlx330 FPGA on our self-designed PCI-Express card, reaching a sustained performance of 8.50 GFLOPS at 133 MHz, which outperforms previous work.

关键词： Field programmable gate arrays Matrix decomposition Hardware Power engineering computing Algorithm design and analysis Linear algebra Computer applications Concurrent computing Distributed computing Laboratories

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An Irregular cutting based distributed mapping algorithm for DVE systems

An Irregular cutting based distributed mapping algorithm for...

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Pacific-Asia Workshop on Computational Intelligence and Industrial Application, PACIIA

作者： Wei Zhang Hangjun Zhou Yuxing Peng Sikun Li Min Xi National Laboratory of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha China Department of Computer Science Xi'an Jiaotong University Xi'an China

Distributed Virtual Environment (DVE) systems have become more and more important both in academic communities and the industries. To guarantee the load constrain, the physical world integrity and the virtual world integrity, the virtual environment should be divided into several parts and mapped to multiple servers, which are located in geographically different places. Many centralized algorithms based on regular cutting method are proposed to solve this problem. However, the dynamic property of clients and distributed property of the system make the existing algorithms unable to undertake it. In this paper, we propose a metric to measure the cutting quality and design a distributed mapping algorithm based on an irregular cutting. Simulation results show that our algorithm greatly decreases the costs of DVE systems for migration of clients and effectively improves the satisfaction degree of users.

关键词： Defense industry Virtual environment Computer industry Computer science Algorithm design and analysis Delay Partitioning algorithms Industrial training Computational intelligence Application software

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Optimizing Reference Gene Set for Inter-Chip Normalization Using Genetic Algorithm

Optimizing Reference Gene Set for Inter-Chip Normalization U...

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International Conference on BioMedical Engineering and Informatics (BMEI)

作者： Fei Li Wenjian Xu Peng Li XiaoChen Bo Yuxing Peng Department of Computer Science National Laboratory of Parallel & Distributed Processing National University of Defense Technology Changsha China Beijing Institute of Radiation Medicine Beijing China

Due to the existence of systematic bias in the measurements, inter-chip normalization is required before integrated data analysis of multiple microarray datasets. Current inter-chip normalization methods rely on some assumptions, which can rarely be verified by experiments, such as the invariant expression level of housekeeping genes or the stability of statistical data distribution. In this paper, we present a highly verifiable inter-chip normalization method using genetic optimization algorithm, which depends only on a small number of housekeeping genes, and therefore facilitates experimental validation without any accuracy lost.

关键词： Genetic algorithms Gene expression Laboratories Data analysis Optimization methods Genomics Bioinformatics Statistical distributions Probes Computer science

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Optimization and Performance Modeling of Stencil Computations on ARM Architectures

Optimization and Performance Modeling of Stencil Computation...

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IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Kaifang Zhang Huayou Su Peng Zhang Yong Dou National Key Laboratory for Parallel and Distribution Processing National University of Defense Technology Changsha China CAEP Software Center for High Performance Numerical Simulation Beijing China Institute of Applied Physics and Computational Mathematics Beijing China

Stencil Computation has long been an omnipresent kernel of a wide range of scientific and engineering applications. There is much work investigating the stencil performance on x86 processors and accelerators such as GPU. Meanwhile, ARM processors for HPC have been highlighted more and more with Fugaku of Japan becoming the first number one system on the TOP-500 list. In this paper, we focus on modeling and optimizing the performance of stencil computation on ARM architectures. Specifically, we proposed a performance model for stencil computation based on tiling optimization to guide the optimal configuration of tiling parameters for good cache reuse. We validate the proposed model with the Performance Monitor Unit (PMU) provided by the ARM processor. Experimental results show that the prediction error of the execution time can be lower to 1.37%. Furthermore, we can achieve a maximum of 1.26 × speedup compared to the naive implementation according to the optimization parameters provided from the model.

关键词： Computational modeling High performance computing Conferences Graphics processing units Computer architecture Phasor measurement units Kernel

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HybridSwap: A scalable and synthetic framework for guest swapping on virtualization platform

HybridSwap: A scalable and synthetic framework for guest swa...

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IEEE Annual Joint Conference: INFOCOM, IEEE Computer and Communications Societies

作者： Pengfei Zhang Xi Li Rui Chu Huaimin Wang National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China School of Information Science and Engineering Central South University Changsha China

In IaaS cloud environments, peak memory demand caused by hotspot applications in Virtual Machine (VM) often results in performance degradation within and outside of this VM. Some solutions such as host swapping and ballooning for memory consolidation and overcommitment have been proposed. These solutions, however, have no help for addressing guest swapping issues inside VM. Even though host holds sufficient memory pages, guest OS is unable to utilize free pages in host directly due to the semantic gap between VMM and it. Our goal is to alleviate the performance degradation by decreasing disk I/O operations generated by guest swapping. Based on the insight analysis of behavioral features of guest swapping, we design HybridSwap, a distributed scalable framework which organize surplus memory in all hosts within data center into virtual pools for swapping. This framework builds up a synthetic swapping mechanism in a peer-to-peer way, which VM can adaptively choose suitable pools for swapping. We implement the prototype of HybridSwap and evaluate it with different benchmarks. The results demonstrate that our solution has the ability to promote the guest swapping efficiency indeed. Even in some cases, it shows 2-5 times of performance promotion compared with the baseline setup.

关键词： Benchmark testing Virtualization Semantics Servers Operating systems Degradation Instruction sets

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Enhancing Temporal Alignment with Autoencoder Regularization

Enhancing Temporal Alignment with Autoencoder Regularization

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International Joint Conference on Neural Networks

作者： Liquan Nie Yuanyuan Wang Xiang Zhang Xuhui Huang Zhigang Luo Science and Technology on Parallel and Distributed Processing Laboratory College of Computer National University of Defense Technology Department of Basic Courses Army Officer Academy Department of Computer Science and Technology College of Computer National University of Defense Technology

ISBN: (纸本)9781509006212

Temporal alignment aligns two temporal sequences and is quite challenging due to drastic differences among temporal sequences and source data from different views. Canonical time warping (CTW) has shown great potential in temporal alignment tasks because it can reduce data redundancy by transforming high-dimensional data to a lower-dimensional subspace via canonical correlation analysis (CCA). However, CTW cannot uncover the underlying nonlinear structure embedded in the dataset. In this paper, we propose an autoencoder regularized canonical time warping method (AECTW) to overcome this drawback. Specifically, AECTW enhances lower-dimensional representation of each sequence by incorporating an autoencoder regularization, meanwhile reveals the nonlinear structure of features by explicit nonlinear transformation. By these strategies, AECTW significantly boosts CTW in temporal alignment tasks. Experiments on both synthetic data and two practical human action datasets demonstrate that AECTW outperforms the representative DTW-based methods.

关键词： NONLINEAR STRUCTURES data redundancy Dataset synthetic data Alignment Warping Structural properties Canonical Religious Missions Data sources

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Assessing the Impact of Cascading Failures on the Interdomain Routing System of the Internet

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New Generation Computing 2014年第3期32卷 237-255页

作者： Liu, Yujing Peng, Wei Su, Jinshu Wang, Zhilin College of Computer National University of Defense Technology Hunan Changsha China College of Computer Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Hunan Changsha China Education Department National University of Defense Technology Hunan Changsha China

The Internet is a typical complex network, whose traffic load is controlled by the inter-domain routing system. Due to the co-location of data plane and control plane of Border Gateway Protocol, the survivability of inter-domain routing system is sensitive to severe congestion. Therefore, an initial outage may lead to a cascade of failures in the Internet. But the cascading failures on links are able to be automatically restored when the congestion is mitigated. In this paper, we propose a model - CAFEIN for characterizing this special process. Based on CAFEIN, we assess the difference of impact under intentional attacks and random breakdowns; identify the worst affected part of the Internet; and study the propagation of cascading failures. Through simulations, we find that the cascading failures bring a great deal of added burden to the routing system. However, the cascading effect is amplified globally when the relative capacity of links is very low. Moreover, the difference of impact between intentional attack and random breakdown is not as prominent as previous research due to the unique automatic-restoration process.

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Maximizing Uniform Multicast Throughput in Multi-Channel Dense Wireless Sensor Networks 12

Maximizing Uniform Multicast Throughput in Multi-Channel Den...

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12th International Conference on Mobile Ad-Hoc and Sensor Networks, MSN 2016

作者： Jiao, Xianlong Chen, Guirong Wang, Xiaodong Chen, Yuli Yang, Li Information and Navigation College Air Force Engineering University Xi'an710077 China College of Information System and Management National University of Defense Technology Changsha410073 China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha410073 China Chongqing Guanyinqiao Elementary School Chongqing400020 China Chongqing Liangjiangxinqu Renhe Experimental School Chongqing400021 China

ISBN: (纸本)9781509056965

This paper investigates the problem of maximizing uniform multicast throughput (MUMT) for multi-channel dense wireless sensor networks, where all nodes locate within one-hop transmission range and can communicate with each other on multiple orthogonal channels. This kind of networks show wide application in the real world, and maximizing uniform multicast throughput for these networks is worth deep studying. Previous researches have proved MUMT problem is NP-hard. However, previous researches are either hard to implement, or use too many relay nodes to complete the multicast task, and thus incur high overhead or poor performance. To efficiently solve MUMT problem, we adopt the concept of the maximum independent set with the size constraint, and present one novel Single-Broadcast based Multicast algorithm called SBM based on the concept. We prove that SBM algorithm achieves a constant ratio to the theoretical throughput upper bound. Extensive experimental results demonstrate that, SBM performs better than existing work in terms of both the uniform multicast throughput and the total number of transmissions. © 2016 IEEE.

关键词： Throughput

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Benchmarking the task graph scheduling algorithms

Benchmarking the task graph scheduling algorithms

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International Symposium on parallel processing

作者： Y.-K. Kwok I. Ahmad Parallel Processing Laboratory School of Electrical and Computer Engineering Purdue University West Lafayette IN USA Department of Computer Science Hong Kong University of Science and Technology Hong Kong China

The problem of scheduling a weighted directed acyclic graph (DAG) to a set of homogeneous processors to minimize the completion time has been extensively studied. The NP-completeness of the problem has instigated researchers to propose a myriad of heuristic algorithms. While these algorithms are individually reported to be efficient, it is not clear how effective they are and how well they compare against each other. A comprehensive performance evaluation and comparison of these algorithms entails addressing a number of difficult issues. One of the issues is that a large number of scheduling algorithms are based upon radically different assumptions, making their comparison on a unified basis a rather intricate task. Another issue is that there is no standard set of benchmarks that can be used to evaluate and compare these algorithms. Furthermore, most algorithms are evaluated using small problem sizes, and it is not clear how their performance scales with the problem size. The authors first provide a taxonomy for classifying various algorithms into different categories according to their assumptions and functionalities. They then propose a set of benchmarks which are of diverse structures without being biased towards a particular scheduling technique and still allow variations in important parameters. They have evaluated 15 scheduling algorithms, and compared them using the proposed benchmarks. Based upon the design philosophies and principles behind these algorithms, they interpret the results and discuss why some algorithms perform better than the others.

关键词： Scheduling algorithm Processor scheduling parallel processing Concurrent computing Heuristic algorithms Laboratories Computer science Taxonomy Algorithm design and analysis Scalability

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Accelerating FDTD simulation of microwave pulse coupling into narrow slots on the Intel MIC architecture

Accelerating FDTD simulation of microwave pulse coupling int...

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IEEE Pacific Rim Conference on Communications, Computers and Signal processing

作者： Qinglin Wang Jie Liu Xiantao Cui Guitao Fu Chunye Gong Zuocheng Xing School of Computer Science National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China Beijing Satellite Navigation Center Beijing China

ISBN: (纸本)9781467377898

The coupling of microwaves into apertures plays an important part in many electromagnetic physics and engineering fields. When the width of apertures is very small, Finite Difference Time Domain (FDTD) simulation of the coupling is very time-consuming. As a many-core architecture, the Intel's Many Integrated Core (MIC) architecture owns 512-bit vector units and more than 200 threads. In this paper, we parallelize FDTD simulation of microwave pulse coupling into narrow slots on the Intel MIC architecture. In the implementation, the parallel programming model OpenMP is used to exploit thread parallelism while loop unrolling and SIMD intrinsic functions are utilized to accomplish vectorization. Compared with the serial version on Intel Xeon E5-2670 CPU, the implementation on the MIC coprocessor including 57 cores obtains a speedup of 11.57 times. The experiment results also demonstrate that the parallelization has good scalability in performance. Additionally, how binding relationship between OpenMP threads and hardware threads in MIC influences performance is also reported.

关键词： Microwave integrated circuits Finite difference methods Time-domain analysis Chlorine Hardware

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