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检索条件"机构=Science and Technology on Reliability Physics and Application of Electronic"

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Static thermal resistance test and simulation analysis technology for hybrid microcircuit

Static thermal resistance test and simulation analysis techn...

引用

International Symposium on Advanced Packaging Materials

作者： Bin Zhou Xueli Qi Science and Technology on Reliability Physics and Application of Electronic Component Laboratory CEPREI Guangzhou China School of Electronic and Information Engineering South China University of Technology Guangzhou China

The miniaturization of packaging volume for hybrid microcircuit and the increasing of dissipated power for chip make its junction case thermal resistance parameters become the focus of people's study and attention. The thermal resistance sample was designed based on a new embedded copper enhance case and static measurement was used, transient temperature response curve of internal die was showed by testing, thermal resistance - heat capacity network model was obtained through numerical deconvolution, the thermal resistance of internal structures were analyzed, which was compared with the theory calculation result of 45° method, and the effect of each layer structure on overall junction case thermal resistance was analyzed. In addition, heat dissipation performance was studied by comparative analysis between new case and original cold rolled steel case. Finally, temperature distribution and junction case thermal resistance of new hybrid circuit module were studied by finite element simulation. The results showed that the thermal resistance value of new embedded copper packaging case decreased about 50% in contrast to cold rolled steel case. Decreasing overall internal resistance of microcircuit need improves the heat dissipation performance of case, meanwhile, the effect of each layer structure on whole internal thermal resistance should be decreased as much as possible.

关键词： Thermal resistance Junctions Packaging Thermal analysis electronic packaging thermal management Materials

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The Accelerated Life Experiment Study of Solid State Relay

The Accelerated Life Experiment Study of Solid State Relay

引用

2011 International Conference on Quality,reliability,Risk,Maintenance,and Safety Engineering(2011年质量、可靠性、风险、维修性与安全性国际会议暨第二届维修工程国际学术会议 ICQR2MSE 2011)

作者： Xiaowen ZHANG Hudong ZHANG National Key Laboratory of Science and Technology on Reliability Physics and Application of Electron Institute of Microelectronics School of Electronic and Information EngineeringSouth China University

The operational principle of SSR(Solid State Relay) has been analyzed, and the methods of acceleration life experiments of SSR has been designed. The acceleration life experiment has been conducted under the condition of 125 degree centigrade junction temperature. According to the 0 number device failure in the acceleration life experiment, using unilateral approximate, the lower limit value of MTBF has been calculated under the condition of 90 percent confidence level. If the typical value of 0.7eV active energy for the SSR degradation is choosed in the accelerated life experiment, then the lower limit value of MTBF can be calculated under the condition of 85 degree centigrade junction temperature.

关键词： Solid State Relay reliability failure mechanism acceleration life experiments

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The Effect of Thermal Stress on High Density Packaging Integrated Circuits

The Effect of Thermal Stress on High Density Packaging Integ...

引用

2011 International Symposium on Advanced Packaging Materials(2011年先进电子封装材料国际会议APM)

作者： Bin Yao Ping Lai Jian Liu Xiaosi Liang Science and Technology on Reliability Physics and Application of Electronic Component Laboratory China Electronic Product Reliability and Environmental Testing Research Institute No.110 Dongguanzhuang Rd Guangzhou Guangdong P.R. China

The trend of electronics industry is toward advanced high density packaging technologies. The reliability of integrated circuits (ICs) which is significantly affected by thermal stress has become more essential as the packaging density increases. In this paper, an accelerated thermal reliability test method for evaluating the packaging reliability of ICs which includes hot step, cold step and rapid thermal cycling test is presented. The technology of FIMV (Force current measure voltage) was applied during the reliability test as an indicator of degradation of packaging property, which allowed the reliability performance of ICs to be assessed in real time. The experimental results showed that the thermal stress resulted in the degradation of interfacial adhesion of plastic packaging ICs. Because of the temperature changing during the rapid thermal test, the strain and stress due to the coefficient of thermal expansion (CTE) mismatch between the encapsulant and the adjacent materials could contribute to delamination or de-adhesion. In some cases it was directly linked to a failure if some severe defects occured because of delamination, such as wire bond lift-off or fracture. Crack in die attach adhesive based on the same failure mechanism was also found. Additionally, unwanted brittle Au-Al intermetallic compound was detected at the bond interface because of the effect of high temperature. The formation of the Au-Al intermetallic compound led to the increase of electrical resistance and the weakening of bond strength which resulted in bond lift-off finally. At last future research work in this field is suggested.

关键词： reliability electronic packaging thermal management Thermal stresses Packaging Stress Delamination Compounds

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A power analysis based approach to detect Trojan circuits

A power analysis based approach to detect Trojan circuits

引用

International Conference on Quality, reliability, Risk, Maintenance, and Safety Engineering (ICQR2MSE)

作者： Li-Wei Wang Hong-Wei Luo School of Electronic and Information Engineering South China University of Technology Guangzhou China Science and Technology on Reliability Physics and Application of Electronic Component Laboratory CEPREI Laboratories Guangzhou China

Because of globalization of the semiconductor industry, the IC fabrication is increasingly outsourced. This poses a significant risk for integrated circuits (ICs) used for security critical applications. Attackers can maliciously alter the ICs during fabrication in untrusted foundries. In the case of ICs bought externally, they may have hidden functions that users would never know. These malicious alterations and hidden functions are also referred to as “Hardware Trojan”. It is extremely difficult to discover such Trojan circuits using conventional testing strategies. In this paper, we propose a nondestructive, power analysis based Trojan detection approach which is able to detect Trojan circuits in the presence of large noise. The approach is validated using 90nm FPGA (Xilinx Spartan-3E) chips. Experimental results with a 64-bit Data Encryption Standard (DES) cipher circuit show that Trojans which are 2 orders of magnitude smaller than the DES circuit can be detected by using statistic signal processing techniques.

关键词： Trojan horses Hardware Field programmable gate arrays Power measurement Payloads

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Pre-designed Prognostic cells for host circuits reliability monitoring

Pre-designed Prognostic cells for host circuits reliability ...

引用

2011 International Conference on Electric Information and Control Engineering, ICEICE 2011

作者： Lu, Yu-Dong En, Yun-Fei Luo, Hong-Wei Wan, Ming Natl. Key Lab. of Sci. and Technology on Reliability Physics and Application of Electronic Component 5th Electronics Research Institute Ministry of Industry and Information Technology Guangzhou 510610 China Key Laboratory of Specially Functional Materials College of Materials Science and Engineering South China University of Technology Guangzhou 510640 China

ISBN: (纸本)9781424480395

CMOS integrated circuits have certain defined failure mechanisms that can contribute to end-of-life failure. These failure mechanisms include time dependent dielectric breakdown, electromigration, hot carrier injection and so on. All of these common failure modes are far worse at geometries below 0.18 m. The traditional reliability predictions for integrated circuits are inaccurate because they do not account for the actual environments that the circuits are subjected to in its life cycle. Prognostics is a method that enables monitoring the state of reliability of a product in real time, and therefore can be used to provide advance warning of a failure, to provide condition based maintenance and to help in IC design and development. Pre-designed Prognostic cells are incorporated into integrated circuits to provide advance warning of failure for specific wear-out failure mechanisms. The time to failure of these prognostic cells can be pre-calibrated with respect to the time to failure of the host circuit. The accurate failure prediction and the remaining luseful life for specfic failure mechanism were achieved from the prognostic cell with the proper prognostic distance. © 2011 IEEE.

关键词： reliability

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Optimal Buffering Resources Allocation of On-Chip Networks with Finite Buffers

Optimal Buffering Resources Allocation of On-Chip Networks w...

引用

International Workshop on Intelligent Networks and Intelligent Systems (ICINIS)

作者： Li-Wei Wang Science and Technology on Reliability Physics and Application of Electronic Component Laboratory The 5th Electronics Research Institute Ministry of Industry and Information Technology Guangzhou China

A novel buffer allocation algorithm for deterministically-routed and wormhole-switched network-on-chip (NoC) with finite size buffers is proposed. Based on a analytical model, the algorithm can assess the performance bottleneck of all the NoC routers. When the total buffer budget is fixed, according to the traffic characteristics of the target application, the proposed algorithm automatically allocates the buffer depth for each input channel in different routers. The simulation results show that, by using the proposed algorithm, better system performance and lower average packet latency can be achieved compared to the uniform assignment of buffering resources which has been widely adopted in current NoC design.

关键词： Resource management System-on-a-chip Analytical models System performance Mathematical model Routing Queueing analysis

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Effect of substrate material on thermal reliability of high-power electronic packaging device

Effect of substrate material on thermal reliability of high-...

引用

2011 International Symposium on Advanced Packaging Materials(2011年先进电子封装材料国际会议APM)

作者： Fang fang Song Ping Lai Science and Technology on Reliability Physics and Application of Electronic Component Laboratory China Electronic Product Reliability and Environmental Testing Research Institute No. 110 Dongguanzhuang Rd. Tianhe District 510610 Guangzhou china

Thermal performance and reliability are necessary to be considered for high-power electronic packaging device design. In this paper, the thermal characteristic of one kind of packaging device was studied using FEM and experimentation, for phase shifter. The model for thermal condition of phase shifter was established. The top junction temperature obtained by simution shows tendency as tested experiment results, verifying the correctness of the simulation model and method used. The relation of relative temperature rising to different substrate thickness and material is studied by *** quantitative relations of these parameters and temperature provided a theoretical basis for the thermal design and reliability estimate, the optimization of parameters and the reliability improvement of phase shifter.

关键词： Substrates electronic packaging thermal management Thermal analysis Phase shifters Junctions reliability

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A Study of Solder Joint Degradation and Detection Using RF Impedance Analysis

A Study of Solder Joint Degradation and Detection Using RF I...

引用

2011 International Symposium on Advanced Packaging Materials(2011年先进电子封装材料国际会议APM)

作者： Bin Yao Yudong Lu Ming Wan Science and Technology on Reliability Physics and Application of Electronic Component Laboratory China Electronic Product Reliability and Environmental Testing Research Institute No.110 Dongguanzhuang Rd Guangzhou Guangdong P.R. China

The trend of many types of electronic products is toward higher operating frequencies. At high frequencies, the signal propagation is concentrated at the surface of interconnects, which is known as the skin effect. Therefore, even a samll crack at the surface of a solder joint may directly influence the performance of high speed electronic assemblies. Degradation of solder joints, such as cracking due to fatigue or stress, generally initiates at the surface where the strain range is maximized, and propagates inward. Traditional DC resistance measurements are not able to sense partial cracks in solder joints. RF impedance analysis, which is capable of detecting small cracks, offers an improved means of monitoring the degradation of solder joints of high speed electronic products. In this study, RF impedance changes are used as an early indicator of degradation of solder joints, due to the skin effect, compared with DC resistance measurements. Impedance-controlled circuit boards on which surface mount components were soldered have been developed. Partially and entirely cracked solder joints were produced for test in advance. The RF impedance was observed to increase in response to partial cracking of the solder joint, while the DC resistance did not indicate any anomalies. The technique of RF impedance analysis shows potential as a prognostic tool that can provide advanced warning of impending failures of solder joint. At last future research work in this field is suggested.

关键词： Soldering Impedance Radio frequency Degradation Resistance Monitoring Time domain analysis

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Weld technology reliability analysis of Cathode in Vacuum Tube

Weld Technology Reliability analysis of Cathode in Vacuum Tu...

引用

2011 International Symposium on Advanced Packaging Materials(2011年先进电子封装材料国际会议APM)

作者： Xian-long Feng Shajin Li Fang fang Song Shiji Yu Science and Technology on Reliability Physics and Application of Electronic Component Laboratory Chi Institutes of Electronics No.110 Dongguanzhuang Rd. Tianhe District 510610 Guangzhou china

Influence of weld technology on reliability and life to cathode in vacuum tube was studied by requests of microwave tube. The quality of weld technology quite affects the emission capability of cathode. The mode of weld quite affects thermal efficiency of cathode in vacuum tube. Thermal efficiency of cathode can increase availably by changing the weld technology on the heat transfer path. Thermal analysis and optimization design of cathode module for vacuum tube was carried out with the FEM in order to obtain required cathode temperature with lower heat power. The weld mode quite affects the cathode heat power, for example, the cathode heat power can reduce 28.6 ％ with 8+8 laser spot welding. We have also built the life test system of TWT's electron gun structure of 8 +8 laser spot welding, using this life test system, up to 30 years life of cathode is forecasted.

关键词： Cathodes Welding Electron tubes reliability Thermal analysis Resistance heating

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Effect of Fixation Method on Solder Joint Vibration Fatigue reliability of High Density PCB Assembly

Effect of Fixation Method on Solder Joint Vibration Fatigue ...

引用

2011 12th International Conference on electronic Packaging technology & High Density Packaging(2011 电子封装技术与高密度封装国际会议)

作者： Xueli QI Yunfei EN Bin ZHOU Guoyuan LI Pengfei Zhang School of Electronic and Information Engineering South China University of Technology Address:No.381 Science and Technology on Reliability Physics and Application of Electronic Component Laboratory CE School of Electronic and Information Engineering South China University of Technology Address:No.381

In order to explore the influence of various fixation method on vibration fatigue reliability of high density PCB assembly, a three-dimensional simulation model which was almost completely in keeping with test samples was created, and the modal parameters were obtained through modal test and finite element method respectively. Based on the verification of FEM Model correctness, through designed different fixation methods, random vibration finite element simulation was being done, and vibration parameters were picked up and analyzed. The result showed that more PCB fixations could increase the first frequency, decrease the deformation of PCB. Under the same conditions, the order of the first frequency of the PCB Assembly with different fixation methods is: one end fixation ＜two screws fixation＜two ends fixation＜four screws fixation＜six screws fixation. Consequently, more PCB fixations will decrease stress of key positions of PCB assembly, and BGA (ball grid array) devices should be placed near the region which has more fixation *** stress of solder joint is located in the outermost corner of central PBGA module, and the accurate interface of maximum stress is located on the BGA side. And stress increases with the distance between solder and the center of BGA. So, the dimensional structure of PBGA assembly, fixation method of PCB and chip position should be considered comprehensively when vibration reliability of PBGA assembly was analysized. Finally, it can make some references for guiding BGA placement, selecting the appropriate size of BGA and the best fixation method for predicting and optimizing random vibration fatigue life of solder joints.

关键词： Vibrations Stress Soldering Analytical models Fatigue Fasteners

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