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Effects of Thick Al Wires Bonding Layout on reliability of Power Devices

Effects of Thick Al Wires Bonding Layout on Reliability of P...

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2011 International Conference on Quality,reliability,Risk,Maintenance,and Safety Engineering(2011年质量、可靠性、风险、维修性与安全性国际会议暨第二届维修工程国际学术会议 ICQR2MSE 2011)

作者： Hailong LIU Shaohua YANG Wulei TANG Gangtao ZHENG School of Electronic and Information Engineering South China University of Technology Science and Te Science and Technology Laboratory on Reliability Physics and Application of Electronic Component Gua Guangdong Soft-Park Co. Ltd Guangzhou China School of Electronic and Information Engineering South China University of Technology Guangzhou Chi

The maximum avalanche energy that the power MOSFET devices can sustain is primarily determined by the device design and manufacturing process. However, the layout of the thick Al wires on the source pad of the chip also has some influences on it. In this research, two different MOSFETs (400V/5.5A;75V/75A) were chosen and two or three Al wires were bonded with different layouts to investigate the influence of the configuration of thick Al wires bonding on the avalanche reliability of the power devices. The maximum single pulse avalanche energy (EAS) was employed to evaluate the devices’ avalanche reliability. The avalanche test results revealed that the wires’ layout has no obvious influence on the EAS for the low current MOSFET devices, while has significant influence on that for high current MOSFET devices. The more closely the Al wires distributed, the lower the EAS was obtained. Results also reveal that when devices suffer the maximum EAS, its average junction temperature (TJ) would be lower if the wires have a closer distribution. The avalanche breakdown spot tends to locate at the position around the Al wire, especially the area under the bonding. These results show that the Al wires on source electrode pad of the MOSFET should be distributed as uniformly as possible to optimize the avalanche reliability of the devices.

关键词： component power device wires bonding reliability leadframe

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New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory

New SEC-DED-DAEC codes for multiple bit upsets mitigation in...

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IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Zhu Ming Xiao Li Yi Luo Hong Wei Microelectronics Center Harbin Institute of Technology Harbin China Reliability Physics and Application Technology of Electrical Component National Key Laboratory of Science and Technology Guangzhou China

Nowadays, multiple bit upsets (MBUs) have been widely investigated in memories. Conventional single error correction and double error detection (SEC-DED) codes are capable of correcting one error and detecting all possible double errors. However, they may not provide adequate protection against MBUs. This paper proposes new single-error-correction, double-error-detection double-adjacent-error-correction (SEC-DED-DAEC) codes to mitigate radiation or noise source induced MBUs in memories. The proposed SEC-DED-DAEC codes are obtained from conventional SEC-DED codes according to the mathematics model established in this paper. They can detect and correct all adjacent double bit errors and assure a lower miscorrection probability for non-adjacent double bit errors compared with other SEC-DED-DAEC codes. Furthermore, the redundancy bits of the proposed scheme are the same as those of conventional SEC-DED codes. This means that the increase of correct-capability do not cause additional hardware overhead for the memory system. Finally, the experiment results reveal that the proposed scheme reduces the miscorrection probability of non-adjacent double bit errors by 12% compared to the best known SEC-DED-DAEC codes. Moreover, compared to the well known BCH codes, the proposed scheme reduces 40% hardware redundancy and keeps an acceptable reliability.

关键词： Vectors Mathematical model Equations reliability Decoding Logic gates

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Design EG-LDPC codes for soft error mitigation in memory

Design EG-LDPC codes for soft error mitigation in memory

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Academic International Symposium on Optoelectronics and Microelectronics technology (AISOMT)

作者： Xiao Li Yi Zhu Ming Zhang Yan Jing Luo Hong Wei Microelectronics Center Harbin Institute of Technology Harbin China Reliability Physics and Application Technology of Electrical Component National Key Laboratory of Science and Technology Guangzhou China

As the feature sizes of integrated circuits decreasing, single event transient (SET) in combinational circuits can not been ignored any longer. In this paper, a novel fault-secure scheme for memory has been proposed by studying the structural features of Euclidean Geometry-Low Density Parity Check (EG-LDPC) codes. The proposed fault-secure scheme can tolerate transient faults both in the storage cell and in the encoder and decoder, using the parallel majority decoding and the feedback loop structure. In order to improve the decoding speed, an algorithm is presented, which can reduce the majority decoding of EG-LDPC codes into two steps. Furthermore, the proposed scheme can suit ordinary data width (e.g., 2 n bits) in memory. Finally, the correcting capability and the reliability of the proposed scheme are analyzed. The experiment results reveal that the Mean Time to Failure (MTTF) of the proposed scheme is 419%, 104% and 118% compared with that of Hamming code, Matrix code and Reed-Muller code, respectively.

关键词： Decoding Vectors Circuit faults Parity check codes Generators reliability Detectors

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The Popcorn Effect of Lead and Lead-free Mixed Assembly Process In High Density Plastic Packages

The Popcorn Effect of Lead and Lead-free Mixed Assembly Proc...

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2011 International Symposium on Advanced Packaging Materials(2011年先进电子封装材料国际会议APM)

作者： Xiao Hong Ping Lai Science and Technology on Reliability Physics and Application of Electronic Component Laboratory The 5th Electronics Research Institute of the Ministry of Industry and Information Technology No. 110 Dongguanzhuang Rd Guangzhou Guangdong PR. China

The expansion of integrated circuit applications is driving chip costs down. To respond to the lower price the lower price expectations, manufacturers bring Plastic packages which is cost less expensive packaging solutions. Today although the electronic packaging industry there are still many enterprises were to have lead solder, but this does not preclude the "lead-free" has become the main topic of electronic materials and microelectronics. In this transitional period, lead and lead-free both assemble on the plastic package in the field of application is already unavoidable. Problem existed in lead or leadfree materials, technology, equipment, system compatibility and other issues. The reliability of the plastic package IC is becoming a key concern. The popcorn effect is caused when moisture inside a plastic package turns to steam and expands rapidly during infrared and vapor phase reflow solder process. Under certain conditions, the force from the expanding moisture can cause stresses inside the package. Solder ball inside with lead process and outside with lead-free may result in failure. It is prompted by the melting point of lead and lead-free material is different in the same BGA packaging chip. In most severe cases, the packaging defects and the stress may result in external package cracks. And in this paper, a sample is given that the BGA packaging chip exist void in the die/die attach interface. Capillary phenomenon is present in the package closest to the die attach, and lead to a short circuit between some pins. Pay more attention to the reliability of mixed assembly process is of great value.

关键词： Lead Plastics Delamination reliability Packaging Compounds

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A Study of junction temperature testing method in GaAs PHEMT

A Study of junction temperature testing method in GaAs PHEMT

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2011 International Symposium on Advanced Packaging Materials(2011年先进电子封装材料国际会议APM)

作者： Xiao Hong Yun Huang Shajin Li Science and Technology on Reliability Physics and Application of Electronic Component Laboratory The 5th Electronics Research Institute of the Ministry of Industry and Information Technology No.110 Dongguanzhuang Rd Guangzhou Guangdong P.R. China

With the development of the RF/microwave technology, more and more GaAs PHEMT device is used and the power of the device is also increasing. However, the test of thermal performance and heat dissipation in packaging device is still a prominent problem. In order to obtain steady operation and longer lifetime, what is the highest temperature environment the device can work? Also the package of the device is a major factor of cooling effect, so the measurement of thermal resistance must be accurate. In this paper, some methods was given to measuring of device junction temperature. Traditional test method such as infrared thermography is not work for the packaging device. A new method to measure the thermal resistance of GaAs PHEMT is given. Based on the electrical measurement method for thermal resistance and Schottky junction temperature of GaAs PHEMT and the factors which influence measuring results are investigated. In the meantime we design the setup of the test system for the measuring. The first is drawing the curve of forward voltage changes and temperature. Then the thermal resistance is measured and calculated. The error introduced by thermal resistance of GaAs PHEMT surface is eliminated. The experimental results show that the method has the advantages of simple structure and good stability. The proposed method is capable to evaluate the thermal resistance of the packaging device such as GaN device, VDMOS and so on. It is very significant to provide evaluation method in reliability test.

关键词： Temperature measurement Junctions Thermal resistance Gallium arsenide PHEMTs Electrical resistance measurement

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application of Fault Simulation Test in the VLSI Failure Analysis

Application of Fault Simulation Test in the VLSI Failure Ana...

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作者： Qingzhong XIAO Xiaoling LIN Ruohe YAO National Key Laboratory of Science and Technology on Reliability Physics and Application of Electric Institute of Microelectronics Schoolof Electron and Information Engineering South China University o

Purpose of VLSI failure analysis is to find effective measure to eliminate or reduce the same failure to happen again. But failure mechanism or failure mode of VLSI is variety. If the VLSI failure analyzer can not find out the root cause, wrong prevention method may be adapted and failure may still happen next time. This paper introduces fault simulation test, which is an effective way to distinguish the similar failure mechanism and confirm the failure mode, such as latch-up effect, electric over stress (EOS), etc. It can provide useful reference information for the users or producers. At the same time, several typical failure analysis cases are used to show how the fault simulation test works.

关键词： fault simulation test failure analysis latch-up contamination

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The Common Failure Mechanisms of Plastic Encapsulated Devices Induced by Package Defect

The Common Failure Mechanisms of Plastic Encapsulated Device...

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2011 12th International Conference on electronic Packaging technology & High Density Packaging(2011 电子封装技术与高密度封装国际会议)

作者： Yuan Chen Ping Li Science and Technology on Reliability Physics and Application of Electronic Component Laboratory The Fifth Electronics Research Institute of Ministry of Industry and Information Technology Address: No.110 Dongguanzhuang Road Tianhe District Guangzhou Guangdong P.R.China

Plastic encapsulated devices are gaining wide acceptance due to advantages in size, weight, cost, availability, performance, and state of-the-art technology and design. However, the long-term reliability of plastic encapsulated devices is influenced by the inherent structures and materials. The paper introduced three common failure mechanisms of plastic encapsulated devices induced by package defect: interfacial delamination, poor die attachment and poor encapsulation material. The failure mechanisms were illuminated by theories combining with cases.

关键词： Delamination Plastics reliability Compounds Microassembly Lead

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Solder Joint Degradation Analysis Using Time Domain Reflectometry

Solder Joint Degradation Analysis Using Time Domain Reflecto...

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作者： Ming WAN Yudong LU Jingdong FENG Xiaohan WANG Yunfei EN Bin YAO Xin WANG College of Materials Science and Engineering South China University of Technology Guangzhou China S College of Materials Science and Engineering South China University of Technology Guangzhou China S Science and Technology on Reliability Physics and Application of Electronic Component Laboratory The Key Laboratory of Specially Functional Materials College of Materials Science and Engineering Sout

Solder joints on the Printed-Circuit board (PCB) serve as mechanical and electrical connections. Their function maybe simple, but the reliability of the solder joints may affect the entire device or system. They are usually the weak links when the electronic products are exposed to a variety of load conditions from their operation and storage, such as temperature cycling, vibration, shock and humidity. One of the most important parameters of solder joints is electrical stability. The resistance or impedance will rise as the fracture spreads through the solder joints. The reliability of solder joints is often determined through continuous DC resistance measurement, but it not very sensitive. In recent years, Time Domain Reflectometry (TDR) technique has been found to be a better alternative that are required for monitoring the degradation of interconnects. At high frequencies, signal propagation is concentrated at the surface of interconnects, a phenomenon known as the skin effect. Degradation of interconnects, such as cracking of solder joints due to fatigue or shock loading, also usually initiates at the surface and propagates inward. Therefore, even a small crack at the surface of a solder joint may change RF impedance. A physical crack initiated at the surface of the solder joints results in the increase of RF impedance. Thus, the crack length should be correlative with RF impedance or Reflection Coefficient, and the failure time of the solder joint could be estimated in view of electronic theory and the theory of fracture. A mathematic model was proposed to predict the relationship between the time domain reflection coefficient of solder joint and the crack length in it.

关键词： Solder joint reliability Time domain reflect degradation

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Strain Tears the Phonon Band of Graphene

Strain Tears the Phonon Band of Graphene

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第三届亚洲光谱会议

作者： X.X.Yang J.W.Li Y.Wang Z.F.Zhou Chang Q.Sun Institute for Quantum Engineering and Micro-Nano Energy Technology Key Laboratory of Low-Dimensional Materials and Application Technologiesand Faculty of Materials and Optoelectronic PhysicsXiangtan University School of Information and Electronic Engineering Hunan University of Science and Technology School of Electrical and Electronic Engineering Nanyang Technological University

Theoretical[1]duplication of the measured Raman shifts of the monolayer graphene under the uniaxial strain has derived the effective force constant of 6.28 N/m of the C-C bond and clarifies that:i)the bond elongation ... 详细信息

关键词： Strain Tears the Phonon Band of Graphene

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Raman spectroscopic determination of the length,strength,compressibility,Debye temperature,elasticity,and force constant of the C-C bond in graphene

Raman spectroscopic determination of the length,strength,com...

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第三届亚洲光谱会议

作者： X.X.Yang J.W.Li Z.F.Zhou Y.Wang L.W.Yang W.T.Zheng Chang Q.Sun Institute for Quantum Engineering and Micro-Nano Energy Technology Key Laboratory of Low-Dimensional Materials and Application Technologiesand Faculty of Materials and Optoelectronic PhysicsXiangtan University School of Information and Electronic Engineering Hunan University of Science and Technology Department of materials Science Jilin University School of Electrical and Electronic Engineering Nanyang Technological University

From the perspective of bond relaxation and vibration,we have been able to reconcile the Raman shift of graphene under stimuli of the number-of-layer,the uniaxial-strain,the pressure,and the temperature in terms of th... 详细信息

关键词： Raman spectroscopic determination of the length,strength,compressibility,Debye temperature,elasticity,and force constant of the

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