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Unified virtual memory support for deep CNN accelerator on soC FPGA 1

15th International Conference on Algorithms and Architectures for parallel processing, ICA3PP 2015

作者： Xiao, Tao Qiao, Yuran Shen, Junzhong Yang, Qianming Wen, Mei College of Computer National University of Defense Technology Changsha410073 China National Key Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha410073 China

ISBN: (数字)9783319271194

ISBN: (纸本)9783319271187

Cooperation of CPU and hardware accelerator on SoC FPGA to accomplish computational intensive tasks, provides significant advantages in performance and energy efficiency. However, current operating systems provide little support for accelerators: the OS is unaware that a computational task can be executed either on a CPU core or an accelerator, and provides no assistance in efficient management of data sharing between CPU and accelerator on the DRAM, such as zero copy, data coherence. It’s also hard for current OS to allocate large contiguous physical memory space for accelerator. In this paper, we select the Xilinx ZYNQ as target and qualitatively analyze methods of sharing data. Besides using high-performance (HP) AXI interfaces of the ZYQN device, we develop a novel memory management system for FPGA-based accelerator. It provides a unified virtual space for CPU cores and accelerator so that they can access the same memory space in the operating systems user space. For a deep convolutional neural network task, our design gains up to speed-up of 5. 34x compared to traditional processoraccelerator cooperation. © Springer International Publishing Switzerland 2015.

关键词： Energy efficiency

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Comparing performance of hierarchical identity-based signature schemes

Comparing performance of hierarchical identity-based signatu...

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作者： Chen, Peixin Wu, Yilun Su, Jinshu Wang, Xiaofeng College of Computer National University of Defense Technology Changsha410073 China National Key Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha410073 China

The key escrow problem and high computational cost are the two major problems that hinder the wider adoption of hierarchical identity-based signature (HIBS) scheme. HIBS schemes with either escrow-free (EF) or online/offline (OO) model have been proved secure in our previous work. However, there is no much EF or OO scheme that has been evaluated experimentally. In this letter, several EF/OO HIBS schemes are considered. We study the algorithmic complexity of the schemes both theoretically and experimentally. Scheme performance and practicability of EF and OO models are discussed. © Copyright 2016 The Institute of Electronics, Information and Communication Engineers.

关键词： Computational complexity

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A Dynamic Mapping Model for General CNN Accelerator Based on FPGA 17th

A Dynamic Mapping Model for General CNN Accelerator Based on...

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17th IFIP WG 10.3 International Conference on Network and parallel Computing, NPC 2020

作者： Zhao, Xiaoqiang Jiang, Jingfei Han, Zhe Xu, Jinwei Liu, Zhiqiang National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China Artificial Intelligence Research Center National Innovation Institute of Defense Technology Beijing China

ISBN: (纸本)9783030794774

As the application scenarios of convolutional neural network (CNN) become more and more complex, the general CNN accelerator based on matrix multiplication has become a new research focus. The existing mapping methods for converting convolution calculation into matrix multiplication need to be improved. This paper proposes a new dynamic mapping model to improve the flexibility and versatility of matrix multiplication. The dynamic mapping model implements two algorithms: dynamic residue processing mapping algorithm (DRPMA) and dilated convolution mapping algorithm (DCMA). The former can dynamically adjust the mapping method according to the number of output channels of the convolution layer, improve the utilization of the multiply-accumulate (MAC) array. The latter extends the efficient support for Dilated CNNs. For demonstration, we implement an accelerator with Verilog on Xilinx VC709 FPGA board and test some typical CNN models. Experimental results show that the general accelerator achieves high performance and energy efficiency. © 2021, IFIP International Federation for Information processing.

关键词： Field programmable gate arrays (FPGA)

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Controllable Template Generation for Document-level Event Extraction 4

Controllable Template Generation for Document-level Event Ex...

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4th International Conference on Neural Networks, Information and Communication Engineering, NNICE 2024

作者： Fang, Quntian Liu, Feng Huang, Zhen Guo, Zhenliang Wang, Changjian Li, Dongsheng Hu, Minghao National University of Defense Technology National Key Laboratory of Parallel and Distributed Processing Changsha China Academy of Military Sciences Information Research Center Beijing China

ISBN: (纸本)9798350394375

Document-level event extraction task has achieved significant progress based on template generation methods. However, there is no reasonable regulation and restriction in the existing template-based generation methods, which results in the uncontrollability of the generation results. In some scenarios, model generates entities that do not belong to the input text, or generate template content repeatedly. It is determined by the nature of the extraction task and the generation task. To this end, we propose a controllable template generation event extraction model. According to the characteristics of template generation and event extraction tasks, the model devises copy mechanism, inhibition mechanism and rejection mechanism under the appropriately constructed template. Our model achieves state-of-the-art result on MUC-4 dataset, and finally through experimental analysis, it demonstrates the effectiveness of each mechanism we proposed. © 2024 IEEE.

关键词： Extraction

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The detection and assessment of possible RNA secondary structure using multiple sequence alignment

Proceedings of the ACM Symposium on Applied Computing

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Proceedings of the ACM Symposium on Applied Computing 2007年 133-137页

作者： Fang, Xiaoyong Wang, Zhenghua Luo, Zhigang Yuan, Bo Ding, Fan National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China Department of Biomedical Informatics College of Medicine and Public Health Ohio State University Columbus OH 43210-1239 United States

ISBN: (纸本)1595934804;9781595934802

We here devise a new method for detecting and assessing RNA secondary structure by using multiple sequence alignment. The central idea of the method is to first detect conserved stems in the alignment using a special matrix and then assess them by evaluating the ratio of the signal to the noise. We tested the method on data sets composed of pairwise and three-way alignments of known ncRNAs. For the pairwise tests, our method has sensitivity 61.42% and specificity 97.05% for structural alignments, and sensitivity 42.05% and specificity 98.15% for BLAST alignments. For the three-way tests, our method has sensitivity 65.17% and specificity 97.96% for structural alignments, and sensitivity 40.70% and specificity 97.87% for CLUSTALW alignments. Our method can detect conserved secondary structures in gapped or ungapped RNA alignments. Copyright 2007 ACM.

关键词： RNA

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VAWS: Constructing trusted open computing system of mapreduce with verified participants

VAWS: Constructing trusted open computing system of mapreduc...

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作者： Ding, Yan Wang, Huaimin Wei, Lifeng Chen, Songzheng Fu, Hongyi Xu, Xinhai School of Computer National University of Defense Technology Changsha HN China National Laboratory for Parallel and Distributed Processing National Univ. of Defense Technology Changsha HN China

MapReduce is commonly used as a parallel massive data processing model. When deploying it as a service over the open systems, the computational integrity of the participants is becoming an important issue due to the untrustworthy workers. Current duplication-based solutions can effectively solve non-collusive attacks, yet most of them require a centralized worker to re-compute additional sampled tasks to defend collusive attacks, which makes the worker a bottleneck. In this paper, we try to explore a trusted worker scheduling framework, named VAWS, to detect collusive attackers and assure the integrity of data processing without extra re-computation. Based on the historical results of verification, we construct an Integrity Attestation Graph (IAG) in VAWS to identify malicious mappers and remove them from the framework. To further improve the efficiency of identification, a verification-couple selection method with the IAG guidance is introduced to detect the potential accomplices of the confirmed malicious worker. We have proven the effectiveness of our proposed method on the improvement of system performance in theoretical analysis. Intensive experiments show the accuracy of VAWS is over 97% and the overhead of computation is closed to the ideal value of 2 with the increasing of the number of map tasks in our scheme. Copyright © 2014 The Institute of Electronics, Information and Communication Engineers.

关键词： MapReduce

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A systematic review of structured sparse learning

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Frontiers of Information technology & Electronic Engineering 2017年第4期18卷 445-463页

作者： Lin-bo QIAO Bo-feng ZHANG Jin-shu SU Xi-cheng LU College of Computer National University of Defense Technology Changsha 410073 China National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

High-dimensional data arising from diverse scientific research fields and industrial development have led to increased interest in sparse learning due to model parsimony and computational advantage. With the assumption of sparsity, many computational problems can be handled efficiently in practice. Structured sparse learning encodes the structural information of the variables and has been quite successful in numerous research fields. With various types of structures discovered, sorts of structured regularizations have been proposed. These regularizations have greatly improved the efficacy of sparse learning algorithms through the use of specific structural information. In this article, we present a systematic review of structured sparse learning including ideas, formulations, algorithms, and applications. We present these algorithms in the unified framework of minimizing the sum of loss and penalty functions, summarize publicly accessible software implementations, and compare the computational complexity of typical optimization methods to solve structured sparse learning problems. In experiments, we present applications in unsupervised learning, for structured signal recovery and hierarchical image reconstruction, and in supervised learning in the context of a novel graph-guided logistic regression.

关键词： Sparse learning Structured sparse learning Structured regularization

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Identifying faults in large-scale distributed systems by filtering noisy error logs

Identifying faults in large-scale distributed systems by fil...

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Workshop on Proactive Failure Avoidance, Recovery, and Maintenance

作者： Rao, Xiang Wang, Huaimin Shi, Dianxi Chen, Zhenbang Cai, Hua Zhou, Qi Sun, Tingtao National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China Computing Platform Alibaba Cloud Computing Corporation Hangzhou China

ISBN: (纸本)9781457703751

Extracting fault features with the error logs of fault injection tests has been widely studied in the area of large scale distributed systems for decades. However, the process of extracting features is severely affected by a large amount of noisy logs. While the existing work tries to solve the problem by compressing logs in temporal and spatial views or removing the semantic redundancy between logs, they fail to consider the co-existence of other noisy faults that generate error logs instead of injected faults, for example, random hardware faults, unexpected bugs of softwares, system configuration faults or the error rank of a log severity. During a fault feature extraction process, those noisy faults generate error logs that are not related to a target fault, and will strongly mislead the resulted fault features. We call an error log that is not related to a target fault a noisy error log. To filter out noisy error logs, we present a similarity-based error log filtering method SBF, which consists of three integrated steps: (1) model error logs into time series and use haar wavelet transform to get the approximate time series;(2) divide the approximate time series into sub time series by valleys;(3) identify noisy error logs by comparing the similarity between the sub time series of target error logs and the template of noisy error logs. We apply our log filtering method in an enterprise cloud system and show its effectiveness. Compared with the existing work, we successfully filter out noisy error logs and increase the precision and the recall rate of fault feature extraction.1 © 2011 IEEE.

关键词： Errors

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A novel L1 cache based on volatile STT-RAM 20th

A novel L1 cache based on volatile STT-RAM

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20th Annual Conference on Computer Engineering and technology, NCCET 2016

作者： Hongguang, Zhang Minxuan, Zhang College of Computer National University of Defense Technology Changsha410073 China National Key Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha410073 China

ISBN: (纸本)9789811031588

Spin-transfer torque random access memory (STT-RAM) is one of the most promising substitutes for universal main memory and cache due to its excellent scalability, high density and low leakage power. Nevertheless, the current non-volatile STT-RAM cache architecture also has some drawbacks, such as long write latency and high write energy, which limit the application of STTRAM in the top level cache design. To solve these problems, we relax the retention time of STT-RAM to explore its different write performance, and propose a novel STT-RAM L1 cache architecture implemented with volatile STT-RAM as well as its related refresh scheme. The performance of proposed design is the same as SRAM L1 cache while its overall power consumption is only 63.8% of the latter one. © Springer Nature Singapore Pte Ltd. 2016.

关键词： Static random access storage

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A neuro-genetic approach for inferring gene regulatory networks from gene expression data 22

A neuro-genetic approach for inferring gene regulatory netwo...

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Proceedings of the 9th International Conference on Bioinformatics Research and Applications

作者： Guo Mao Zhengbin Pang Jie Liu Ke Zuo Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology China

ISBN: (纸本)9781450396868

Accurate prediction of gene regulation rules is important for understanding complex life processes. Existing computational algorithms designed for bulk transcriptome datasets typically require a large number of time points to infer gene regulatory networks (GRNs), are suitable for a small number of genes, and cannot efficiently detect potential regulatory relationships. We propose an approach based on a deep learning framework to reconstruct GRNs from bulk transcriptome datasets, assuming that the expression levels of transcription factors involved in gene regulation are strong predictors of the expression of their target genes. The algorithm uses multilayer perceptrons to infer the regulatory relationship between multiple transcription factors and a gene, and uses genetic algorithms to search for the best regulatory gene combination. The results show that our approach is more accurate than other methods for reconstructing gene regulatory networks on real-world and simulated bulk transcriptome gene expression datasets.

关键词： gene regulatory networks datasets multilayer perceptrons genetic algorithms

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