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Congress on Image and Signal processing, CISP

作者： Yuan, Jie Wu, Jian-Ping Wang, Zheng-Hua National Lab. of Parallel and Distributed Processing National University of Defense Technology Changsha China School of Computer Science National University of Defense Changsha China

ISBN: (纸本)9781424465149

This paper presents a high performance parallel formulation for 1-D FFT based on transpose algorithm. The parallel scheme of FFT trades off some efficiency for a more consistent level of parallel performance. It involves matrix transposition, and a new in-place transposing algorithm is introduced into the parallel matrix transposition to improve the efficiency. Depending on the size of the input n, the number of processes p, and the memory or network bandwidth, this method can achieve better parallel performance than the other on cluster of SMP architectures. Test shows us that our scheme can achieve a good speedup. ©2010 IEEE.

关键词： Fast Fourier transforms

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Research on accelerating CEE-DGCNN event extraction algorithm based on multi-CPU platform 2

Research on accelerating CEE-DGCNN event extraction algorith...

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2020 2nd International Conference on Electronics and Communication, Network and Computer technology, ECNCT 2020

作者： Li, Yan Jiang, Jinfei Xu, Jinwei Gao, Zikai Dou, Yong Zhou, Haifang Science and Technology on Parallel and Distributed Laboratory National University of Defense Technology Changsha410005 China Department of Computational Science National University of Defense Technology Changsha410005 China

With the development of the Internet, the volume of information is expanding rapidly, and the complex information makes it particularly important to extract information quickly and intelligently. Event extraction algorithm is such a kind of fast and accurate information acquisition algorithm. With the development of deep learning in recent years, deep learning also shines in the field of time extraction. CEE-DGCNN network is an efficient and accurate event extraction algorithm for Chinese text. At present, the acceleration research on deep learning in the academic community mainly focuses on GPU, FPGA and other platforms. In fact, compared with these platforms, CPU is more versatile. Considering that the algorithm should have universality and universality in industrial application, this paper makes an in-depth analysis of CEE-DGCNN algorithm to study its acceleration on CPU. Experiments were carried out on x86 and ARM architectures respectively, and good acceleration effects were achieved. © 2020 Published under licence by IOP Publishing Ltd.

关键词： Extraction

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Predicting potential gene ontology from cellular response data 17

Predicting potential gene ontology from cellular response da...

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5th International Conference on Bioinformatics and Computational Biology, ICBCB 2017

作者： Hong, Hao Yin, Xiaoyao Li, Fei Guan, Naiyang Bo, Xiaochen Luo, Zhigang Department of Chemistry and Biology National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China Department of Biotechnology Beijing Institute of Radiation Medicine Beijing China

ISBN: (纸本)9781450348270

Ontologies have proven to be useful for capturing and organizing knowledge as a hierarchical set of terms and their relationships. However, curating gene ontology data by hand requires specialized knowledge of certain field, which is inefficient. Thus inferring gene ontology from the exponentially increased biological data is getting hot. Based on the Library of Integrated Network-Based Cellular Signatures (LINCS) data we came up with the hypothesis that genes participate in analogous biological processes might affect cells accordantly. By assessing cellular response after genes were knock out we built a similarity matrix with the Gene Set Enrichment Analysis (GSEA) and clustered the genes with affinity propagation algorithm. Next we mapped the cluster result to gene ontology biological process data for annotation and enrichment analysis, which confirmed our hypothesis and made it possible to predict biological processes for unannotated genes from cellular response data after genes are knock out for the first time. We further validated the rationality from the gene ontology molecular function data. © 2017 ACM.

关键词： Gene Ontology

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A mathematical model for empowerment of Beowulf clusters for exascale computing

A mathematical model for empowerment of Beowulf clusters for...

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2013 11th International Conference on High Performance Computing and Simulation, HPCS 2013

作者： Mirtaheri, Seyedeh Leili Khaneghah, Ehsan Mousavi Grandinetti, Lucio Sharifi, Mohsen Center of High Performance Computing for Parallel and Distributed Processing University of Calabria Rende Italy School of Computer Engineering Iran University of Science and Technology Tehran Iran

ISBN: (纸本)9781479908363

High-performance computing (HPC) clusters are currently faced with two major challenges - namely, the dynamic nature of new generation of applications and the heterogeneity of platforms - if they are going to be useful for exascale computing. Processes running these applications may well demand unpredictable requirements and changes to system configuration and capabilities at runtime, thereby requiring fast system response without sacrificing the transparency and integrity of the reconfigured empowered system that is running on a heterogeneous platform. While a challenge in and of itself, platform heterogeneity is both useful and instrumental in the handling of unpredictable requests. The realization of such a dynamically reconfigurable and heterogeneous HPC cluster system for exascale computing requires a model to guide running processes to determine if they need empowerment of the current cluster, and if yes, by how much. To show the feasibility of empowerment of traditional HPC clusters for exascale computing, we have selected Beowulf as a noble candidate cluster and present a mathematical model for the empowerment of Beowulf clusters for exascale computing (EBEC). We have developed the model in line with Beowulf's cluster approach and by using vector space algebra. In contrast to traditional hardware-oriented approaches to improvise the performance of clusters, we use a software approach to the development of the proposed model by emphasizing processes, which act as the creators of the cluster and thus should decide on system (re)configuration, as the principal building blocks of the system. We have also adopted a new approach to heterogeneity by considering heterogeneity at different levels including hardware, system software, application software, and system functionality. In addition to support for heterogeneity and dynamic reconfiguration, the proposed model includes support for scalability that is crucial to exascale computing too. © 2013 IEEE.

关键词： Vector spaces

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RiverMapper: Step-wisely Mapping the Surface Rivers on Optical Remote Sensing Images

RiverMapper: Step-wisely Mapping the Surface Rivers on Optic...

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2022 International Conference on Neural Networks, Information, and Communication Engineering, NNICE 2022

作者： Zhang, Peng Pan, Hengyue Yang, Ke Dou, Yong Niu, Xin National Laboratory for Parallel and Distributed Processing National University of Defense Technology 410073 China Artificial Intelligence Research Center National Innovation Institute of Defense Technology BeiJing100850 China

ISBN: (纸本)9781510655171

Accurately mapping the surface rivers is important in ecological environment monitoring and disaster prevention. The development of remote sensing technology and computer vision greatly improves the efficiency of this task. However, there are few methods that map the rivers from an image directly. The existing automatic river mapping methods usually had two successive stages: waterbody extraction and flow-path extraction, where the latter methods were very dependent on the waterbody masks generated by the former methods. Errors in waterbody masks caused breaks and redundancies in the extracted graphs. This paper proposed RiverMapper, which mapped the rivers step-wisely without dividing into two stages. Following the directions and actions predicted by the convolution neural network, RiverMapper walked along the rivers step by step and cropped the fixed-size image patches at each step for segmentation. Final river graphs were constructed by the waterbody mask patches and those tracks generated by RiverMapper. We applied RiverMapper on optical remote sensing images containing the Changjiang River and the Huanghe River. Without the degradation of the performance on waterbody extraction, RiverMapper outperformed other methods in terms of the local topological and geometrical similarity between the predicted and the ground-truth river graphs. © 2022 SPIE.

关键词： Mapping

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The parallelized Cuckoo Filter for Cold Data Representation 23

The Parallelized Cuckoo Filter for Cold Data Representation

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23rd IEEE International Conference on High Performance Computing and Communications, 7th IEEE International Conference on Data science and Systems, 19th IEEE International Conference on Smart City and 7th IEEE International Conference on Dependability in Sensor, Cloud and Big Data Systems and Applications, HPCC-DSS-SmartCity-DependSys 2021

作者： Sun, Bowen Luo, Lailong Li, Shangsen Chen, Yingwen Guo, Deke College of Computer National University of Defense Technology China National University of Defense Technology Science and Technology on Information Systems Engineering Laboratory China College of Computer National University of Defense Technology National Lab for Parallel and Distributed Processing China

ISBN: (纸本)9781665494571

Cold data contributes a large portion of the big data today and is usually stored in secondary storage. Various sketch data structures are implemented to represent the stored elements and provide constant-time membership queries. Considering the large volume and infrequent access of cold data, we envision three rationales of cold data representation: 1) parallelized insertion, 2) accurate representation, and 3) constant-time query/deletion. The existing sketches, however, fail to achieve these rationales simultaneously. To this end, we propose a novel sketch named parallelized cuckoo Filter (PCF) in this paper. PCF divides the standard cuckoo filter into multiple homogenous segments. An additional hash function is introduced to assign an element to a segment. The element will be inserted into the selected segment. With such a design, element insertions in PCF can be naturally parallelized. Besides, as a variant of the cuckoo filter, PCF naturally realizes the accurate representation and constant-time query/deletion requirements. Comprehensive experiments further indicate that PCF achieves the three rationales simultaneously. © 2021 IEEE.

关键词： Hash functions Smart cities Big Data Data structures Standards

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A Deeply Pipelined 64-bit Multiplier for High-Performance RISC-V Processors 6

A Deeply Pipelined 64-bit Multiplier for High-Performance RI...

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6th International Conference on Frontier Technologies of Information and Computer, ICFTIC 2024

作者： Liu, Wenyi Hu, Feng Li, Guilan Xu, Bangjian Niu, Xin College of Computer Science and Electronic Hunan University Changsha China College of Computer National University of Defense Technology Science and Technology on Parallel and Distributed Laboratory Changsha China

ISBN: (纸本)9798331541750

The multiplier is an important component of the processor's computing unit. Multiplication, multiplication, addition, and multiplication and subtraction operations are widely used in various signal processing algorithms. Based on this, this article extends the multiplication instructions of RISC-V, designs a 64-bit multiplier that combines the booth2 algorithm and wallace compression technology, and designs a deep pipeline mechanism for the multiplier to improve performance. Finally, Through logical simulation and emulation, the result output is correct. Comprehensive results show that under the 28nm cmos process, the MAC unit can reach 2.22Ghz. © 2024 IEEE.

关键词： Pipeline processing systems

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The acceleration of turbo decoder on the newest GPGPU of Kepler architecture

The acceleration of turbo decoder on the newest GPGPU of Kep...

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International Symposium on Communications and Information Technologies (ISCIT)

作者： Yang Zhang Zuocheng Xing Luechao Yuan Cang Liu Qinglin Wang Science and technology on Parallel and distributed processing laboratory National University of Defense Technology ChangSha China

ISBN: (纸本)9781479944156

In the paper, a new implementation of a 3GPP LTE standards compliant turbo decoder based on GPGPU is proposed. It uses the newest GPU-Tesla K20c, which is based on the Kepler GK110 architecture. The new architecture has more powerful parallel computing capability and we use it to fully exploit the parallelism in the turbo decoding algorithm in novel ways. Meanwhile, we use various memory hierarchies to meet various kinds of data demands on speed and capacity. Simulation shows that our implementation is practical and it gets 76% improvement on throughput over the latest GPU implementation. The result demonstrates that the newest Kepler architecture is suitable for turbo decoding and it can be a promising reconfigurable platform for the communication system.

关键词： Decoding Graphics processing units parallel processing Computer architecture Throughput Kernel Bit error rate

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Exploiting contention and congestion aware switch allocation in network-on-chips 17

Exploiting contention and congestion aware switch allocation...

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50th ACM Turing Conference - China, ACM TUR-C 2017

作者： Li, Cunlu Dongy, Dezun Liao, Xiangke National Laboratory for Parallel and Distributed Processing Collaborative Innovation Center of High Performance Computing College of Computer National University of Defense Technology Changsha Hunan410073 China

ISBN: (纸本)9781450348737

Network-on-chip system plays an important role to improve the performance of chip multiprocessor systems. As the complexity of the network increases, congestion problem has become the major performance bottleneck and seriously influence the performance of NoCs. Prior works have focused on designing effective routing algorithm based on collecting congestion and contention information to load balance the traffic. However, most prior works do not consider balancing the traffic load during switch allocation. Due to the lack of congestion information in switch allocation stage, switch allocator performs allocation only based on packet requests and thus aggravates the congestion in the ports of switch. In this paper, we propose to add the congestion and contention information into the switch allocation process and design an efficient on-chip switching strategy which utilizes the contention and congestion information to load balance the traffic and achieve efficient switch allocation. To further enhance the performance of our design, we carefully design our switch allocation strategy to balance the trade-off between traffic load balance and the matching efficiency in switch allocation. We evaluate our design under synthetic traffic and trace of parsec benchmarks. Our evaluations show this mechanism achieves optimal latency compared to best previous switch allocation strategies. © 2017 ACM.

关键词： Network-on-chip

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Evaluating matrix multiplication-based convolution algorithm on multi-core digital signal processors

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Guofang Keji Daxue Xuebao/Journal of National University of Defense technology 2023年第1期45卷 86-94页

作者： Wang, Qinglin Pei, Xiangdong Liao, Linyu Wang, Haoxu Li, Rongchun Mei, Songzhu Li, Dongsheng College of Computer Science and Technology National University of Defense Technology Changsha410073 China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha410073 China

The matrix multiplication-based convolutional algorithm, which can efficiently implement convolutions with different parameters, is the first choice of convolution performance optimization for a given chip. Based on the architecture of Phytium heterogeneous multi-core DSPs(digital signal processors) developed by National University of Defense technology and the characteristic of the matrix multiplication-based convolutional algorithm, a parallel implementation of the matrix multiplication-based convolutional algorithm (called ftmEConv) for different convolutions on multi-core DSPs was proposed. The ftmEConv consists of four parallelized parts(input feature maps transformation, filter transformation, matrix multiplication, and output feature maps transformation), all of which were optimized for multi-core DSPs, and the performance of each part was improved by effectively exploiting the potential of all functional units in DSP cores. The experimental results demonstrate that ftmEConv achieves computational efficiency of up to 42.90%. Compared with other implementations of the matrix multiplication-based convolutional algorithm on heterogeneous chips, ftmEConv gets a speedup of up to 7.79 times. © 2023 National University of Defense technology. All rights reserved.

关键词： Convolution

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