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23rd IEEE International Conference on High Performance Computing and Communications, 7th IEEE International Conference on Data science and Systems, 19th IEEE International Conference on Smart City and 7th IEEE International Conference on Dependability in Sensor, Cloud and Big Data Systems and Applications, HPCC-DSS-SmartCity-DependSys 2021

作者： Sun, Bowen Luo, Lailong Li, Shangsen Chen, Yingwen Guo, Deke College of Computer National University of Defense Technology China National University of Defense Technology Science and Technology on Information Systems Engineering Laboratory China College of Computer National University of Defense Technology National Lab for Parallel and Distributed Processing China

ISBN: (纸本)9781665494571

Cold data contributes a large portion of the big data today and is usually stored in secondary storage. Various sketch data structures are implemented to represent the stored elements and provide constant-time membership queries. Considering the large volume and infrequent access of cold data, we envision three rationales of cold data representation: 1) parallelized insertion, 2) accurate representation, and 3) constant-time query/deletion. The existing sketches, however, fail to achieve these rationales simultaneously. To this end, we propose a novel sketch named parallelized cuckoo Filter (PCF) in this paper. PCF divides the standard cuckoo filter into multiple homogenous segments. An additional hash function is introduced to assign an element to a segment. The element will be inserted into the selected segment. With such a design, element insertions in PCF can be naturally parallelized. Besides, as a variant of the cuckoo filter, PCF naturally realizes the accurate representation and constant-time query/deletion requirements. Comprehensive experiments further indicate that PCF achieves the three rationales simultaneously. © 2021 IEEE.

关键词： Hash functions Smart cities Big Data Data structures Standards

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A Deeply Pipelined 64-bit Multiplier for High-Performance RISC-V Processors 6

A Deeply Pipelined 64-bit Multiplier for High-Performance RI...

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6th International Conference on Frontier Technologies of Information and Computer, ICFTIC 2024

作者： Liu, Wenyi Hu, Feng Li, Guilan Xu, Bangjian Niu, Xin College of Computer Science and Electronic Hunan University Changsha China College of Computer National University of Defense Technology Science and Technology on Parallel and Distributed Laboratory Changsha China

ISBN: (纸本)9798331541750

The multiplier is an important component of the processor's computing unit. Multiplication, multiplication, addition, and multiplication and subtraction operations are widely used in various signal processing algorithms. Based on this, this article extends the multiplication instructions of RISC-V, designs a 64-bit multiplier that combines the booth2 algorithm and wallace compression technology, and designs a deep pipeline mechanism for the multiplier to improve performance. Finally, Through logical simulation and emulation, the result output is correct. Comprehensive results show that under the 28nm cmos process, the MAC unit can reach 2.22Ghz. © 2024 IEEE.

关键词： Pipeline processing systems

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The acceleration of turbo decoder on the newest GPGPU of Kepler architecture

The acceleration of turbo decoder on the newest GPGPU of Kep...

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International Symposium on Communications and Information Technologies (ISCIT)

作者： Yang Zhang Zuocheng Xing Luechao Yuan Cang Liu Qinglin Wang Science and technology on Parallel and distributed processing laboratory National University of Defense Technology ChangSha China

ISBN: (纸本)9781479944156

In the paper, a new implementation of a 3GPP LTE standards compliant turbo decoder based on GPGPU is proposed. It uses the newest GPU-Tesla K20c, which is based on the Kepler GK110 architecture. The new architecture has more powerful parallel computing capability and we use it to fully exploit the parallelism in the turbo decoding algorithm in novel ways. Meanwhile, we use various memory hierarchies to meet various kinds of data demands on speed and capacity. Simulation shows that our implementation is practical and it gets 76% improvement on throughput over the latest GPU implementation. The result demonstrates that the newest Kepler architecture is suitable for turbo decoding and it can be a promising reconfigurable platform for the communication system.

关键词： Decoding Graphics processing units parallel processing Computer architecture Throughput Kernel Bit error rate

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Exploiting contention and congestion aware switch allocation in network-on-chips 17

Exploiting contention and congestion aware switch allocation...

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50th ACM Turing Conference - China, ACM TUR-C 2017

作者： Li, Cunlu Dongy, Dezun Liao, Xiangke National Laboratory for Parallel and Distributed Processing Collaborative Innovation Center of High Performance Computing College of Computer National University of Defense Technology Changsha Hunan410073 China

ISBN: (纸本)9781450348737

Network-on-chip system plays an important role to improve the performance of chip multiprocessor systems. As the complexity of the network increases, congestion problem has become the major performance bottleneck and seriously influence the performance of NoCs. Prior works have focused on designing effective routing algorithm based on collecting congestion and contention information to load balance the traffic. However, most prior works do not consider balancing the traffic load during switch allocation. Due to the lack of congestion information in switch allocation stage, switch allocator performs allocation only based on packet requests and thus aggravates the congestion in the ports of switch. In this paper, we propose to add the congestion and contention information into the switch allocation process and design an efficient on-chip switching strategy which utilizes the contention and congestion information to load balance the traffic and achieve efficient switch allocation. To further enhance the performance of our design, we carefully design our switch allocation strategy to balance the trade-off between traffic load balance and the matching efficiency in switch allocation. We evaluate our design under synthetic traffic and trace of parsec benchmarks. Our evaluations show this mechanism achieves optimal latency compared to best previous switch allocation strategies. © 2017 ACM.

关键词： Network-on-chip

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Evaluating matrix multiplication-based convolution algorithm on multi-core digital signal processors

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Guofang Keji Daxue Xuebao/Journal of National University of Defense technology 2023年第1期45卷 86-94页

作者： Wang, Qinglin Pei, Xiangdong Liao, Linyu Wang, Haoxu Li, Rongchun Mei, Songzhu Li, Dongsheng College of Computer Science and Technology National University of Defense Technology Changsha410073 China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha410073 China

The matrix multiplication-based convolutional algorithm, which can efficiently implement convolutions with different parameters, is the first choice of convolution performance optimization for a given chip. Based on the architecture of Phytium heterogeneous multi-core DSPs(digital signal processors) developed by National University of Defense technology and the characteristic of the matrix multiplication-based convolutional algorithm, a parallel implementation of the matrix multiplication-based convolutional algorithm (called ftmEConv) for different convolutions on multi-core DSPs was proposed. The ftmEConv consists of four parallelized parts(input feature maps transformation, filter transformation, matrix multiplication, and output feature maps transformation), all of which were optimized for multi-core DSPs, and the performance of each part was improved by effectively exploiting the potential of all functional units in DSP cores. The experimental results demonstrate that ftmEConv achieves computational efficiency of up to 42.90%. Compared with other implementations of the matrix multiplication-based convolutional algorithm on heterogeneous chips, ftmEConv gets a speedup of up to 7.79 times. © 2023 National University of Defense technology. All rights reserved.

关键词： Convolution

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Grid computing in China

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Journal of Grid Computing 2004年第2期2卷 193-206页

作者： Yang, Guangwen Jin, Hai Li, Minglu Xiao, Nong Li, Wei Wu, Zhaohui Wu, Yongwei Tang, Feilong Department of Computer Science and Technology Tsinghua University Beijing China School of Computer Huazhong University of Science and Technology Wuhan China Department of Computer Science and Engineering Shanghai Jiao Tong University Shanghai China Key Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China College of Computer Science Zhejiang University Hangzhou 310027 China

Grid computing presents a new trend to distributed computation and Internet applications, which can construct a virtual single image of heterogeneous resources, provide uniform application interface and integrate widespread computational resources into super, ubiquitous and transparent aggregation. In the adoption of Grid computing, China, who is facing more resource heterogeneity and other specific demands, has put much effort on both research and practical utilization. In this paper, we introduce the major China Grid research projects and their perspective applications. First we give the overview of the four government-sponsored programs in Grid, namely the China National Grid, ChinaGrid, NSFC Grid, and ShanghaiGrid. Then we present six representative ongoing Grid systems in details, which are categorized into Grid middleware and Grid application. This paper provides the general picture of Grid computing in China, and shows the great efforts, devotion and confidence in China to use Grid technology to boost the society, economics and scientific research. © Springer 2004.

关键词： Grid computing

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A simulated annealing technique for optimizing timewarp simulation

A simulated annealing technique for optimizing timewarp simu...

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2010 International Conference on Computer Modeling and Simulation, ICCMS 2010

作者： Zhang, Wei Meraji, Sina Wang, Jun Tropper, Carl National Laboratory for Parallel and Distributed Processing School of Computer Science National University of Defense Technology ChangSha 410073 China School of Computer Science McGill University Montreal H3A 2A7 Canada

ISBN: (纸本)9780769539416

According to Moore's law the complexity of VLSI circuits has doubled approximately every two years, resulting in simulation becoming the major bottleneck in the circuit design process. parallel and distributed simulations can be applied as fast, cost effective approaches to the simulation of large, complex circuits. In this paper, a simple yet effective simulated annealing-based approach is proposed to optimize the choice of a time window for optimistic parallel simulation. We chose gate level circuits simulations as our experimental vehicle. Our results show up to a 52% improvement in the simulation time using our simulated annealing algorithm. To the best of our knowledge, this is the first time that SA has been applied to optimize the performance of Time Warp simulations. © 2010 IEEE.

关键词： Simulated annealing

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Topology awareness algorithm for virtual network mapping

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Journal of Zhejiang University-science C(Computers and Electronics) 2012年第3期13卷 178-186页

作者： Xiao-ling LI Huai-min WANG Chang-guo GUO Bo DING Xiao-yong LI Wen-qi BI Shuang TAN National Key Laboratory of Parallel and Distributed Processing National University of Defense Technology.Changsha 410073China School of Computer National University of Defense TechnologyChangsha 410073China China Electronic Systems Engineering Corporation Beijing 100039China The Northern Institute of Electronic Equipment of China Beijing 100083China

Network virtualization is recognized as an effective way to overcome the ossification of the Internet. However, the virtual network mapping problem (VNMP) is a critical challenge, focusing on how to map the virtual networks to the substrate network with efficient utilization of infrastructure resources. The problem can be divided into two phases: node mapping phase and link mapping phase. In the node mapping phase, the existing algorithms usually map those virtual nodes with a complete greedy strategy, without considering the topology among these virtual nodes, resulting in too long substrate paths (with multiple hops). Addressing this problem, we propose a topology awareness mapping algorithm, which considers the topology among these virtual nodes. In the link mapping phase, the new algorithm adopts the k-shortest path algorithm. Simulation results show that the new algorithm greatly increases the long-term average revenue, the acceptance ratio, and the long-term revenue-to-cost ratio (R/C).

关键词： Network virtualization Ossification Virtual network （VN） mapping Substrate network （SN） Topology awareness Acceptance ratio

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Experimental verification of the parasitic bipolar amplification effect in PMOS single event transients

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Chinese Physics B 2014年第7期23卷 775-779页

作者： He Yi-Bai Chen Shu-Ming College of Computer National University of Defense Technology Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology

The contribution of parasitic bipolar amplification to SETs is experimentally verified using two P-hit target chains in the normal layout and in the special layout. For PMOSs in the normal layout, the single-event charge collection is composed of diffusion, drift, and the parasitic bipolar effect, while for PMOSs in the special layout, the parasitic bipolar junction transistor cannot turn on. Heavy ion experimental results show that PMOSs without parasitic bipolar amplification have a 21.4% decrease in the average SET pulse width and roughly a 40.2% reduction in the SET cross-section.

关键词：重离子实验放大效应单事件双极寄生 PMOS 验证瞬态

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Using Document Embedding Techniques for Similar Bug Reports Recommendation

Using Document Embedding Techniques for Similar Bug Reports ...

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IEEE International Conference on Software Engineering and Service sciences (ICSESS)

作者： Ming Chen Dongyang Hu Tao Wang Jun Long Gang Yin Yue Yu Yang Zhang Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

ISBN: (纸本)9781538665664;9781538665657

In the software development, it is common to find that several bug reports are related to many common code files, i.e., similar bugs. Similar bug recommendation is a meaningful task that could assist developers in bug triaging and fixing. If developers can focus on fewer code files, they can fix similar bugs in less time with higher quality. Therefore, building a similar bug recommendation system is a meaningful task that can improve development efficiency. As the state of the art, Yang et al.'s work presented an approach that combines TF-IDF method with Word Embedding model and achieved a good result. To further improve the performance of their approach, in this paper, we propose a novel approach using Document Embedding model. In our preliminary evaluation, we conduct the experiment on the datasets of J dt, Birt and Eclipse platform. And the results show that our approach outperforms Yang et ale `s, with 2.67-9.50% of improvement.

关键词： Computer bugs Task analysis Predictive models Measurement Context modeling Training Software

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