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IEEE International Conference on Data science in Cyberspace (DSC)

作者： Yalong Xie Aiping Li Ziniu Liu Kai Chen Hongkui Tu College of Computer National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory College of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9781665418164

China is a big agricultural county with more than 500 million rural population. In China, farmers usually loan from rural commercial banks or rural credit cooperatives. It is crucial for the national economic development and the improvement of people's standard of living that how to reasonably use funds to subsidize the agricultural population and reduce the risk of rural loans. At present, credit risk prediction of farmers mainly depends on the experience of experts in the business field, and there is little published research on using artificial intelligence methods to solve this problem. This paper presents a complete set of methods, including data collection, feature selection, etc. We propose a novel deep neural network model named DNN-CRP for credit risk prediction of Chinese framers. Experiments on an actual credit loan dataset of Chinese farmers are presented, and experimental results show that the comprehensive performance of the DNN-CRP model is better than current state-of-the-art models. It is believed that the DNN-CRP model proposed in this paper can help banks improve the efficiency of the credit loan business of farmers and reduce credit risks.

关键词： Deep learning Sensitivity Neural networks Sociology Predictive models Data collection Data models

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parallel Implementation of SHA256 on Multizone Heterogeneous Systems

Parallel Implementation of SHA256 on Multizone Heterogeneous...

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IEEE International Conference on Big Data and Cloud Computing (BdCloud)

作者： Yongtao Luo Jie Liu Tiaojie Xiao Chunye Gong Science and Technology on Parallel and Distributed Processing Laboratory Laboratory of Digitizing program for Frontier Equipment National University of Defense Technology Changsha China National Supercomputer Center in Tianjin Tianjin China

SHA-256 plays an important role in widely used applications, such as data security, data integrity, digital signatures, and cryptocurrencies. However, most of the current optimized implementations of SHA-256 are based on CPUs or dedicated hardware, such as ASICs and FPGAs. Consequently, there is a need to explore whether new heterogeneous parallel framework can improve the computational performance of the hash function. To address this issue, we conducted a study on the MT-3000 platform, which is a special architecture processor for the next-generation exascale prototype supercomputer. We proposed MT-SHA256, a heterogeneous multistage parallel implementation for hashing multiple messages on the MT-3000. Combining the architectural features of this processor, we developed an effective solution that significantly improved the computational performance of SHA-256. As a result, MT-SHA256 achieved a maximum throughput of 1045.68 MB/s on a single acceleration core of MT-3000. This is 9.84x higher than the C code implementation on one CPU core of MT-3000. We also performed a scalability test and found that MT-SHA256 achieved a throughput of 98.04 GB/s on a computing node, and extended to 512 nodes (2048 acceleration clusters) on this system with good scalability.

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A Heterogeneous Processor Design for CNN-Based AI Applications on IoT Devices 8

A Heterogeneous Processor Design for CNN-Based AI Applicatio...

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8th International Conference on Identification, Information and Knowledge in the Internet of Things, IIKI 2019

作者： Liu, Zhiqiang Jiang, Jingfei Lei, Guoqing Chen, Kai Qin, Buyue Zhao, Xiaoqiang Artificial Intelligence Research Center National Innovation Institute of Defense Technology Beijing China National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China College of Computer National University of Defense Technology Changsha China College of System Engineering National University of Defense Technology Changsha China

This paper proposes a heterogeneous processor design for CNN-based AI applications on IoT devices. The heterogeneous processor contains an embedded RISC-V CPU that works as a general processor and an efficient CNN-accelerator that supports a variety of CNN models with a list of macro instructions. For demonstration, we implement a prototype on an FPGA platform with the RISC-V CPU working under 20 MHz and the CNN accelerator working under 100 MHz. As a case study, we run a CNN-based face detection and recognition application on this prototype. The prototype can process one image in 0.72 seconds and an ASIC implementation working under 400 MHz can process one image in less than 0.15 seconds by estimation, which can satisfy the needs for many IoT scenarios such as access control systems and check-in systems. © 2020 The Authors. Published by Elsevier B.V.

关键词： Internet of things

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An Optimal Mapping Algorithm Based on Balanced Load Cutting for DVE Systems

An Optimal Mapping Algorithm Based on Balanced Load Cutting ...

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International Symposium on Intelligent Information technology Application, IITA

作者： Wei Zhang Min Xi Hangjun Zhou Yuxing Peng Sikun Li National Laboratory for Parallel and Distributed Processing National University of Defense Technology ChangSha China Department of Computer Science Xi'an Jiaotong University Xi'an China

In distributed virtual environment (DVE) systems, a distributed server infrastructure is often used to reduce the latency between servers and clients. Under this infrastructure, mapping clients to proper servers is one of the key issues for improving the interactivity and overall performance. Most traditional methods of mapping the clients to servers only consider the load balancing problem. However, there are two other important aspects that should be involved: the physical world integrity and the virtual world integrity. In this work, we propose a novel mapping algorithm which takes care of all three aspects at the same time. The algorithm converts the mapping problem into cutting stage and matching stage to get optimal result with polynomial complexity. The experimental results show that our algorithm improves the overall performance of DVE systems significantly.

关键词： Delay Network servers Computer science Virtual environment Load management Polynomials Quality of service Information technology Application software distributed processing

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Differentially Private and Heterogeneity-Robust Federated Learning With Theoretical Guarantee

IEEE Transactions on Artificial Intelligence

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IEEE Transactions on Artificial Intelligence 2024年第12期5卷 6369-6384页

作者： Wang, Xiuhua Wang, Shuai Li, Yiwei Fan, Fengrui Li, Shikang Lin, Xiaodong Huazhong University of Science and Technology Hubei Key Laboratory of Distributed System Security Hubei Engineering Research Center on Big Data Security School of Cyber Science and Engineering Wuhan430074 China University of Electronic Science and Technology of China National Key Laboratory of Wireless Communications Chengdu611731 China Xiamen University of Technology Fujian Key Laboratory of Communication Network and Information Processing Xiamen361024 China University of Guelph School of Computer Science GuelphONN1G 2W1 Canada

Federated learning (FL) is a popular distributed paradigm where enormous clients collaboratively train a machine learning (ML) model under the orchestration of a central server without knowing the clients' private raw data. The development of effective FL algorithms faces multiple practical challenges including data heterogeneity and clients' privacy protection. Despite that numerous attempts have been made to deal with data heterogeneity or rigorous privacy protection, none have effectively tackled both issues simultaneously. In this article, we propose a differentially private and heterogeneity-robust FL algorithm, named DP-FedCVR to mitigate the data heterogeneity by following the client-variance-reduction strategy. Besides, it adopts a sophisticated differential privacy (DP) mechanism where the privacy-amplified strategy is applied, to achieve a rigorous privacy protection guarantee. We show that the proposed DP-FedCVR algorithm maintains its heterogeneity-robustness though DP noises are incorporated, while achieving a sublinear convergence rate for a nonconvex FL problem. Numerical experiments based on image classification tasks are presented to demonstrate that DP-FedCVR provides superior performance over the benchmark algorithms in the presence of data heterogeneity and various DP privacy budgets. © 2020 IEEE.

关键词： Federated learning

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DSDR: Dynamic Semantic Discard Reader for Open-Domain Question Answering

DSDR: Dynamic Semantic Discard Reader for Open-Domain Questi...

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International Joint Conference on Neural Networks

作者： Xu Wang Zhen Huang Yiming Zhang Ludan Tan Yang Liu Science and Technology on Parallel and Distributed Laboratory College of Computer National University of Defense Technology Changsha China

Open-domain question answering (QA) is an important problem in natural language processing. A QA system usually consists of an information retrieve (IR) model for finding the relevant passages that may have answers and a read comprehension (RC) model for generating answers from the selected passages. The state-of-the-art RC model uses all the passages for feature extraction when matching semantic information of text pairs. In this paper, however, we argue that the texts of passages often have different importance for specific questions and some even provide negative information that might affect the correctness of final prediction. To address this problem, we design dynamic semantic discard reader (DSDR), a deep model that tries to drop negative information irrelevant to the questions. The result of our experiment shows that DSDR outperforms existing methods in the exact-match and F1 scores on open-domain QA datasets.

关键词： Semantics Feature extraction Neural networks Encoding TV Task analysis Numerical models

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A Survey on Approaches and Applications of Knowledge Representation Learning

A Survey on Approaches and Applications of Knowledge Represe...

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IEEE International Conference on Data science in Cyberspace (DSC)

作者： Chenchen Li Aiping Li Ye Wang Hongkui Tu Yichen Song College of Computer National University of Defense Technology ChangSha China College of Computer Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology ChangSha China

ISBN: (数字)9781728195582

ISBN: (纸本)9781728195599

Knowledge representation learning (KRL) is one of the important research topics in artificial intelligence and Natural language processing. It can efficiently calculate the semantics of entities and relations in a low-dimensional space, and effectively solve the problem of data sparsity, which significantly improve the performance of knowledge acquisition, fusion and reasoning and so on. Starting from the five perspectives of distance-based, semantic matching, bilinear-based, neural network model and additional information model, this paper first introduces the overall framework and specific model design, and then correspondingly introduces the experimental evaluation tasks, metrics and benchmark datasets of each model. On this basis, how to apply KRL to various downstream tasks is summarized.

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A recursive-adjustment co-allocation scheme in data grid environments 1

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6th International Conference on Algorithms and Architectures for parallel processing, ICA3PP

作者： Yang, Chao-Tung Yang, I.-Hsien Li, Kuan-Ching Hsu, Ching-Hsien High Performance Computing Laboratory Department of Computer Science and Information Engineering Tunghai University Taichung 40704 Taiwan Parallel and Distributed Processing Center Department of Computer Science and Information Management Providence University Taichung 43301 Taiwan Department of Computer Science and Information Engineering Chung Hua University Hsinchu 300 Taiwan

ISBN: (数字)9783540320715

ISBN: (纸本)3540292357

The co-allocation architecture was developed in order to enable parallel downloads of datasets from multiple servers. Several co-allocation strategies have been coupled and used to exploit rate differences among various client-server links and to address dynamic rate fluctuations by dividing files into multiple blocks of equal sizes. However, a major obstacle, the idle time of faster servers having to wait for the slowest server to deliver the final block, makes it important to reduce differences in finish time among replica servers. In this paper, we propose a dynamic co-allocation scheme, namely Recursive-Adjustment Co-Allocation scheme, to improve the performance of data transfer in Data Grids. Our approach reduces the idle time spent waiting for the slowest server and decreases data transfer completion time. © Springer-Verlag Berlin Heidelberg 2005.

关键词： parallel processing systems

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A Simulated Annealing Technique for Optimizing Time Warp Simulation

A Simulated Annealing Technique for Optimizing Time Warp Sim...

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International Conference on Computer Modeling and Simulation, ICCMS

作者： Wei Zhang Sina Meraji Jun Wang Carl Tropper National Laboratory of Parallel and Distributed Processing School of Computer Science National University of Defense Technology ChangSha China School of Computer Science McGill University Montreal Canada

According to Moore's law the complexity of VLSI circuits has doubled approximately every two years, resulting in simulation becoming the major bottleneck in the circuit design process. parallel and distributed simulations can be applied as fast, cost effective approaches to the simulation of large, complex circuits. In this paper, a simple yet effective simulated annealing-based approach is proposed to optimize the choice of a time window for optimistic parallel simulation. We chose gate level circuits simulations as our experimental vehicle. Our results show up to a 52% improvement in the simulation time using our simulated annealing algorithm. To the best of our knowledge, this is the first time that SA has been applied to optimize the performance of time warp simulations.

关键词： Time warp simulation Simulated annealing Circuit simulation Computational modeling Hardware design languages Discrete event simulation Computer simulation Voltage control Concurrent computing Computer science

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Optimizing Irregular-Shaped Matrix-Matrix Multiplication on Multi-Core DSPs

arXiv

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arXiv 2022年

作者： Yin, Shangfei Wang, Qinglin Hao, Ruochen Zhou, Tianyang Mei, Songzhu Liu, Jie Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha410073 China College of Computer National University of Defense Technology Changsha410073 China

General Matrix Multiplication (GEMM) has a wide range of applications in scientific simulation and artificial intelligence. Although traditional libraries can achieve high performance on large regular-shaped GEMMs, they often behave not well on irregular-shaped GEMMs, which are often found in new algorithms and applications of high-performance computing (HPC). Due to energy efficiency constraints, low-power multi-core digital signal processors (DSPs) have become an alternative architecture in HPC systems. Targeting multi-core DSPs in FTm7032, a prototype CPU-DSPs heterogeneous processor for HPC, an efficient implementation - ftIMM - for three types of irregular-shaped GEMMs is proposed. FtIMM supports automatic generation of assembly micro-kernels, two parallelization strategies, and auto-tuning of block sizes and parallelization strategies. The experiments show that ftIMM can get better performance than the traditional GEMM implementations on multi-core DSPs in FT-m7032, yielding on up to 7.2× performance improvement, when performing on irregular-shaped GEMMs. And ftIMM on multi-core DSPs can also far outperform the open source library on multi-core CPUs in FT-m7032, delivering up to 3.1× higher efficiency. Copyright © 2022, The Authors. All rights reserved.

关键词： Digital signal processors

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