Conventional replacement policy LRU(Least Recently Used) can significantly degrade the overall performance of shared cache of Chip Multi-Processors(CMPs), when the aggregate working set of multiple co-scheduled applic...
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Conventional replacement policy LRU(Least Recently Used) can significantly degrade the overall performance of shared cache of Chip Multi-Processors(CMPs), when the aggregate working set of multiple co-scheduled applications can not fit in cache. Different applications have different inherent cache access behavior characteristics. Replacement policy should take into account that fact so as to derive more performance benefit. This paper proposes application cache Behavior Identification based Insertion Policy(BIIP)replacement policies for managing shared cache in CMPs. BIIP seeks to make use of the cache access behavior characteristics of each co-scheduled application to smartly choose replacement policy. Our evaluation using a full system CMP simulator shows that BIIP improves the overall throughput by 14.8%,11.2%, 5.6% and 7.2% on average over baseline LRU policy,the prevailing cache partitioning scheme UCP and two other shared cache replacement policies PIPP, TADIP, respectively on a 4-core CMP with 16 SPEC CPU2006 workloads. Moreover,BIIP requires a total storage overhead of no more than several counters per core, and does not require changes to the current cache structure.
Mining log pattern to analyze the faults in large scale distributed system is affected by the existence of redundant and ambiguous noisy error logs. While existing works try to compress logs in a coarse granularity fr...
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Mining log pattern to analyze the faults in large scale distributed system is affected by the existence of redundant and ambiguous noisy error logs. While existing works try to compress logs in a coarse granularity from temporal and spatial view to remove the redundancy, they fail to reserve those ambiguous logs that might truly relate to a fault, which misleads the fault characterizing result. By modeling error logs as time series and examining the similarity between trash error log template and target error log, the ambiguous error logs are kept and the affected patterns can be effectively removed. Experiments in a practical complex service-based storage show that up to 92% of the affected patterns can be filtered.
Using the graphics processing unit (GPU) to accelerate the general purpose computation has attracted much attention from both the academia and industry due to GPU's powerful computing capacity. Thus optimization o...
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Using the graphics processing unit (GPU) to accelerate the general purpose computation has attracted much attention from both the academia and industry due to GPU's powerful computing capacity. Thus optimization of GPU programs has become a popular research direction. In order to support the general purpose computing more efficiently, GPU has integrated the general data cache to replace the existing software-managed on-chip memory. Consequently, improving the usage of the data cache becomes of vital importance to improve the performance of the GPU programs. The foundation of cache locality optimizations is efficient analysis and prediction of the cache behavior. Unfortunately, existing cache miss analysis models are based on sequential programs and thus cannot be used to analyze the GPU programs directly. In this paper, based on the deep analysis of GPU's execution model, we propose, for the first time, a cache miss analysis model for the GPU programs. We divide the problem into two subproblems: stack distance profile analysis of single thread block and cache contention analysis of multiple thread blocks. The experimental results from nine typical application kernels in the scientific computing field illustrate that our method is efficient and can be used to guide the cache locality optimizations for the GPU programs.
This paper addresses the issue of fault recovery in transactional memory,and proposes a method of fault recovery based on parallel recomputing in transactional memory *** method utilizes the dataversioning mechanism o...
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This paper addresses the issue of fault recovery in transactional memory,and proposes a method of fault recovery based on parallel recomputing in transactional memory *** method utilizes the dataversioning mechanism of transactional memory system to avoid the extra cost of state saving,rolls back a single transaction to avoid wasting the computing time of the fault-free transactions,and adopts the parallel recomputing method to reduce the cost of fault *** paper applies this method to Open TM programs,and proposes the implementation method of parallel recomputing in Open *** last,this paper tests the performance of this method through a test *** experimental results show that,compared with the fault recovery method of rolling back a single transaction,the parallel recomputing method in transactional memory system can execute the fault recovery quickly and accurately and the method has a well scalability.
This work explores the feasibility to implement IEEE-754-2008 standard quadruple precision (Quad) elementary functions on recent FPGAs with plenty of embedded memories and DSP blocks. First, we analysis the implementa...
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This work explores the feasibility to implement IEEE-754-2008 standard quadruple precision (Quad) elementary functions on recent FPGAs with plenty of embedded memories and DSP blocks. First, we analysis the implementation algorithm of Quad elementary functions in detail. Then, we present a special-purpose Very Large Instruction Word (VLIW) architecture for Quad elementary function (QE-Processor). The proposed processor uses a unified hardware structure, equipped with multiple basic arithmetic units, to implement various Quad algebraic and transcendental functions, in which several tradeoffs between latency and resource usage are carefully planned to avoid unbalanced resource utilization. The performance is improved through the explicitly paralleltechnology of custom VLIW instruction. Finally, we create a prototype of QE-Processor into Xilinx Virtex-5 and Virtex-6 FPGA chips. The experimental results show that our design can guarantee that the percentage of correct rounding is more than 99.9%. Moreover, the FPGA implementation on Virtex-6 XC6VLX760-2FF1760 FPGA, running at 220 MHz, outperforms the parallel software approach based on OpenMP running on an Intel Xeon E5620 CPU at 2.40GHz by a factor of 13X-20X for special function applications in Boost library.
Satisfiability Modulo Theories (SMT) is an extension of SAT towards FOL. SMT solvers have proven highly scalable and efficient for problems based on some ground theorems. However, SMT problems involving quantifiers an...
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Satisfiability Modulo Theories (SMT) is an extension of SAT towards FOL. SMT solvers have proven highly scalable and efficient for problems based on some ground theorems. However, SMT problems involving quantifiers and combination of theorems is a long-standing challenge, which has been a major bottleneck of practical application of SMT solvers in some fields. We reveal a decidable fragment of FOL involving quantifiers, which could not be solved by SMT solvers such as Z3, CVC3, etc., and show how to convert them into model checking problems.
Cloud needs to have rapid and elastic resources supply capability, because of the fluctuant resources demand of end-users. Multi-scale resources elastic binding is an important method to provide cloud services with ra...
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Cloud needs to have rapid and elastic resources supply capability, because of the fluctuant resources demand of end-users. Multi-scale resources elastic binding is an important method to provide cloud services with rapid and elastic service capability. The most challenging problem in multi-scale resources elastic binding is how to predict the dynamic resource demand of end-users, and then decide when and to what extent multi-scale resources need elastic binding based on the prediction. In this paper, we present the prediction model based on RBF (Radial Basis Function) Network, which is used to predict end-users resource demand in advance. Compared with current prediction methods, it has faster prediction speed and higher prediction accuracy. Then we use traces data (the bandwidth demand of Web type of cloud services) collected from a real-world cloud provider: ChinaCache, as the training and testing data set to validate the method. Finally, we evaluate the predicted results using general prediction accuracy metrics. The results prove that the prediction model based on RBF network is able to resolve the decision problem in multi-scale resources elastic binding.
Nowadays, the scale of parallel computer systems is increasing, and simulation technology has become an important tool for performance prediction in the system development process. Task mapping approach is an importan...
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Nowadays, the scale of parallel computer systems is increasing, and simulation technology has become an important tool for performance prediction in the system development process. Task mapping approach is an important aspect affecting the performance of simulation. In this paper, in order to solve the task mapping problem in performance simulation, a task mapping algorithm based on simulated annealing is proposed, and we verified the correctness and effectiveness of the algorithm by experiments. Experimental results show that the algorithm has high efficiency, and can solve the large-scale problem with lower time cost.
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