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A data communication scheduler for stream programs on CPU-GPU platform

A data communication scheduler for stream programs on CPU-GP...

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10th IEEE International Conference on Computer and Information technology, CIT-2010, 7th IEEE International Conference on Embedded Software and Systems, ICESS-2010, 10th IEEE Int. Conf. Scalable Computing and Communications, ScalCom-2010

作者： Tang, Tao Xu, Xinhai Lin, Yisong National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9780769541082

In recent years, heterogeneous parallel system have become a focus research area in high performance computing field. Generally,in a heterogeneous parallel system, CPU provides the basic computing environment and special purpose accelerator (GPU in this paper) provides high computing performance. However, the overall performance of the system is prone to be limited by the data communication between the CPU and the GPU. Data communication is typically used to synchronize the array on the CPU and the stream (in AMD's terminology) on the GPU. In many cases, programmers just add data synchronization for each GPU invoking independently. It is easy to program in this manner but much redundant communication may be introduced, which will dramatically degrade the overall performance. To alleviate this problem, based on the stream programming model, we propose a heuristic data communication schedule approach in this paper. By analyzing the state transition of stream/array data pair, relaxing the synchronization strategy conditionally and considering optimization for branch and loop control structure, our approach can significantly reduce the redundant data communication in most cases. © 2010 IEEE.

关键词： Graphics processing unit

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Automatic concurrency management for distributed applications

Automatic concurrency management for distributed application...

引用

15th IEEE Symposium on Computers and Communications, ISCC 2010

作者： Li, Huiba Liu, Shengyun Peng, Yuxing Li, Dongsheng National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424477555

Building distributed applications is difficult mostly because of concurrency management. Existing approaches primarily include events and threads. Researchers and developers have been debating for decades to prove which is superior. Although the conclusion is far from obvious, this long debate clearly shows that neither of them is perfect. One of the problems is that they are both complex and error-prone. Both events and threads need the programmers to explicitly manage concurrency, and we believe it is just the source of difficulties. In this paper, we propose a novel approach-automatic concurrency management by the runtime system. It dynamically analyzes the programs to discover potential concurrency opportunities;and it dynamically schedules the communication and the computation tasks, resulting in automatic concurrent execution. This approach is inspired by the instruction scheduling technologies used in modern microprocessors, which dynamically exploits instruction-level parallelism. However, hardware scheduling algorithms do not fit software in many aspects, thus we have to design a new scheme completely from scratch. automatic concurrency management is a runtime technique with no modification to the language, compiler or byte code, so it is good at backward compatibility. It is essentially a dynamic optimization for networking programs. © 2010 IEEE.

关键词： Scheduling algorithms

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Design and practice on iVCE for memory system

Design and practice on iVCE for memory system

引用

16th IEEE International Conference on parallel and distributed Systems, ICPADS 2010

作者： Chu, Rui Tian, Tian Lin, Zhenli National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9780769543079

As one of the components in iVCE software platform, iVCE/M devotes to the performance improvement of the I/O-intensive and memory-intensive applications with efficient aggregation of distributed memory resources. To facilitate the deployment of iVCE/M, the data locating algorithm with balanced time and space cost, as well as the transparent interface for the legacy applications without code modification, are both significant in the implementation of iVCE/M. We propose the logarithmic search tree based client-side metadata structure to accelerate the data locating using moderate memory consumption, the implicit I/O redirection mechanism, and the implementation of iVCE/M based disk cache system. The experiments with cross domain emulation prove that the scheme is applicable to exploit the distributed memory resources for applications with small granularity I/O accesses. © 2010 IEEE.

关键词： Application programs

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HiAL-Ckpt: A hierarchical application-level checkpointing for CPU-GPU hybrid systems

HiAL-Ckpt: A hierarchical application-level checkpointing fo...

引用

International Conference on Computer science and Education

作者： Xu, Xinhai Lin, Yufei Tang, Tao Lin, Yisong National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424460052

In light of its powerful computing capacity and high energy efficiency, GPU (graphics processing unit) has become a focus in the research field of HPC (High Performance Computing). CPU-GPU heterogeneous parallel systems have become a new development trend of super-computer. However, the inherent unreliability of the GPU hardware deteriorates the reliability of super-computer. We have researched on the fault-tolerance(FT) technique for CPU-GPU heterogeneous parallel systems, and introduced a new checkpointing mechanism, i.e., the hierarchical application-level checkpointing, for such systems. The basic idea of this new checkpointing mechanism is checkpointing at two independent levels, i.e., CPU level and GPU level, to tolerate CPU and GPU faults respectively. Based on the idea, we have also designed and implemented a hierarchical application-level checkpointing tool "HiAL-Ckpt". Using this tool, programmers can insert two kinds of directives, i.e., CPU directives and GPU directives into a program, and the compiler will transform the directives into CPU or GPU checkpointing codes according to their nature. From the case study of SWIM, a test bench from spec2000 benchmark suite, we have demonstrated the validity of the hierarchical application-level checkpointing technique. The experimental results show that the falut-tolerance temporal cost of HiAL-Ckpt for SWIM is only 2.25%, compared with the executing time of SWIM without any FT work. ©2010 IEEE.

关键词： Graphics processing unit

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Mapping OpenMP concepts to the stream programming model

Mapping OpenMP concepts to the stream programming model

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International Conference on Computer science and Education

作者： Tang, Tao Lin, Yisong Ren, Xiaoguang National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424460052

OpenMP is a widely used parallel programming model on traditional multi-core processors. Generally, OpenMP is used to develop fine-grained parallelism through a multithread model. Stream programming model is a new kind of parallel programming model for stream architectures. OpenMP bears a resemblance to the stream programming model at some level. The transformation between the two models has attracted much attention from the research community, since it is the foundation of porting programs between the two architectures. Most related researches focus on the efficiency of porting existing parallel programs to the new architectures such as GPUs. Very few of these studies, however, focus on the portative problem systematically, namely, what kind of parallel programs can be or should be transplanted into stream programs and mapped to run on the stream processors. In this paper, we study the mapping relationship of parallel mechanism in OpenMP to the stream programming model, and point out those parallel mechanisms in OpenMP that are infeasible or undesirable for stream programs. By analyzing two typical benchmarks, we draw the conclusion that a majority of scientific applications are suitable to be mapped to the stream programming model. Our conclusion effectively validates the idea of accelerating scientific applications with the stream processors. ©2010 IEEE.

关键词： Mapping

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Stigmergic collaboration: A sign-based perspective of stigmergy

Stigmergic collaboration: A sign-based perspective of stigme...

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2010 International Conference on Intelligent Computation technology and Automation, ICICTA 2010

作者： Ren, Chuanjun Huang, Hongbing Jin, Shiyao National Laboratory for Parallel and Distributed Processing College of Computer Science National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769540771

Insects build architecturally complex nests and search for remote food by collaboration work despite their limited sensors, minimal individual intelligence and the lack of a central control system. Insets' collaborations emerge as a response of the individual insects to Stigmergy. A sign-based model of Stigmergy to discuss collaboration is proposed in this paper where we picked up "sign" as a key notion to understand it. Therefore, sign is the link of all the components in a Stigmergic complex adaptive system. Based on this understanding, we propose a definition that reveals the nature of signs and exploit the significations and relationships carried by the notion of sign. Then, a sign-based model of Stigmergy is consequently reached, which captures the essentials of Stigmergy. A basic architecture of Stigmergy as well as its constituents are presented and discussed. At last, some applications of the model are discussed. © 2010 Crown Copyright.

关键词： CAS Collaboration Emergence Sign Stigmergy Emergence Volatile Oils Insecta central control system

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Two improved GPU acceleration strategies for force-directed graph layout

Two improved GPU acceleration strategies for force-directed ...

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International Conference on Computer Application and System Modeling

作者： Wang, Yong-Xian Li, Zong-Zhe Yao, Lu Cao, Wei Wang, Zheng-Hua National Key Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424472369

Force directed approach is one of the most widely used methods in graph drawing research. However, the running time is increased intolerablely along with the enlargement of the graph size, which restricts the algorithm's practicability. By the aid of GPU (graphics processing unit) computing platform, we can speed-up the graph layout with low cost, but the existing GPU implementation mainly employees an "one-by-one" style to update the vertex' coordination per iteration, which has a lower convergent rate than the "batch" style which is instead used commonly in traditional CPU implementation. As a result, the aesthetics of graph layout would be decreased if the total running time is restricted. It is hard to achieve both a high speedup factor of GPU over CPU and a high convergent rate in existing GPU computing implementation. In order to solve this problem partially, this paper presents two new strategies to implement the large-scale graph layout on CPU+GPU heteromerous platform to accelerate the force directed layout for graph drawing problem. The numerical computation results show that our GPU implementation can dramatically improve the performance of force-direct layout and is 20 times on a NVIDIA GeForce 9800 GT GPU at 1.44 GHz faster than the one on single-CPU core of Intel Pentium 4 PC at 3.0 GHz for the graph layout with moderate size (typically 1000 vertices). © 2010 IEEE.

关键词： Graphics processing unit

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An efficient load balancing method for constant degree P2P systems

An efficient load balancing method for constant degree P2P s...

引用

2010 International Conference on Computer Design and Applications, ICCDA 2010

作者： Wang, XiaoHai Peng, YuXing Li, DongSheng National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9781424471638

Constant degree P2P systems are turning into the P2P domain's promising hotspot due to their good properties. However, it is often hard to convert a standard constant degree digraph to a flexible DHT schema adapting to dynamic P2P environments. Thus, most research about constant degree P2P focus on DHT's construction and maintenance, while leaving optimization and supporting to upper-layer application behind, such as complex query, load balance, etc. Combining constant degree topology's bit-shift routing schema, we presents an efficient load balancing algorithm based on Reverse Spanning Tree (REST) for constant degree P2P systems. Using the statistic information in joining process, REST judges how many Virtual Servers that a new join super peer can run, and then join all virtual servers evenly and fast with low cost based on the Spanning Tree Peer Set. Experimental results show, without additional data structure, REST keeps the constant degree P2P system load-balanced by assuring each peer of owning a key space proportional to its capability. © 2010 IEEE.

关键词： Trees (mathematics)

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Dynamic program Behavior Identification for high performance CMPs with private LLCs

Dynamic program Behavior Identification for high performance...

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作者： Jia, Xiaomin Lu, Pingjing Sun, Caixia Zhang, Minxuan National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology China

Chip Multi-Processors (CMPs) emerge as a mainstream architectural design alternative for high performance parallel and distributed computing. Last Level Cache (LLC) management is critical to CMPs because off-chip accesses often require a long latency. Due to its short access latency, well performance isolation and easy scalability, private cache is an attractive design alternative for LLC of CMPs. This paper proposes program Behavior Identification-based Cache Sharing (BICS) for LLC management. BICS is based on a private cache organization for the shorter access latency. Meanwhile, BICS tries to simulate a shared cache organization by allowing evicted blocks of one private LLC to be saved at peer LLCs. This technique is called spilling. BICS identifies cache behavior types of applications at runtime. When a cache block is evicted from a private LLC, cache behavior characteristics of the local application are evaluated so as to determine whether the block is to be spilled. Spilled blocks are allowed to replace some valid blocks of the peer LLCs as long as the interference is within a reasonable level. Experimental results using a full system CMP simulator show that BICS improves the overall throughput by as much as 14.5%, 12.6%, 11.0% and 11.7% (on average 8.8%, 4.8%, 4.0% and 6.8%) over private cache, shared cache, Utility-based Cache Partitioning (UCP) scheme and the baseline spilling-based organization Cooperative Caching (CC) respectively on a 4-core CMP for SPEC CPU2006 benchmarks. Copyright© 2010.

关键词： Integrated circuit design

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Nexus: Speculative execution for event-driven networking programs

Nexus: Speculative execution for event-driven networking pro...

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16th IEEE International Conference on parallel and distributed Systems, ICPADS 2010

作者： Li, Huiba Lu, Xicheng Peng, Yuxing National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769543079

The efficiency of communication is a key factor to the performance of networking applications, and concurrent communication is an important approach to the efficiency of communication. However, many concurrency opportunities are very difficult to exploit because they depend on some undeterministic conditions. If these conditions are highly predictable, speculative execution can be a very effective approach to cope with the uncertainties. Existing researches on speculation seldom target at networking systems, and none of them can handle the event-driven model that is very popular in such systems. In this paper, we propose Nexus, a novel speculation scheme that supports event-driven networking applications. Nexus analyzes the dependence relationship of events, and performs speculation according to the duality of events and threads. Evaluation on a prototype implementation of nexus shows that this approach can significantly reduces the time needed to complete an event-driven program. © 2010 IEEE.

关键词： Efficiency

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