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2010 IEEE/ACM International Conference on Green Computing and Communications, GreenCom 2010, 2010 IEEE/ACM International Conference on Cyber, Physical and Social Computing, CPSCom 2010

作者： Wang, Guibin Lin, YiSong Yi, Wei National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9780769543314

As one of the most popular accelerators, Graphics processing Unit (GPU) has demonstrated high computing power in several application fields. On the other hand, GPU also produces high power consumption and has been one of the most largest power consumers in desktop and supercomputer systems. However, software power optimization method targeted for GPU has not been well studied. In this work, we propose kernel fusion method to reduce energy consumption and improve power efficiency on GPU architecture. Through fusing two or more independent kernels, kernel fusion method achieves higher utilization and much more balanced demand for hardware resources, which provides much more potential for power optimization, such as dynamic voltage and frequency scaling (DVFS). Basing on the CUDA programming model, this paper also gives several different fusion methods targeted for different situations. In order to make judicious fusion strategy, we deduce the process of fusing multiple independent kernels as a dynamic programming problem, which could be well solved with many existing tools and be simply embedded into compiler or runtime system. To reduce the overhead introduced by kernel fusion, we also propose effective method to reduce the usage of shared memory and coordinate the thread space of the kernels to be fused. Detailed experimental evaluation validates that the proposed kernel fusion method could reduce energy consumption without performance loss for several typical kernels. © 2010 IEEE.

关键词： Graphics processing unit

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CANSE: A churn adaptive approach to network size estimation

CANSE: A churn adaptive approach to network size estimation

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16th IEEE International Conference on parallel and distributed Systems, ICPADS 2010

作者： Ma, Xing-Kong Wang, Yi-Jie Zheng, Zhong National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9780769543079

Network size is one of the fundamental information of distributed applications. The approach to estimate network size must feature both high accuracy and robustness in order to adapt to the dynamic environment in different topologies. However, existing approaches fail to guarantee accuracy and robustness simultaneously in dynamic topologies due to the randomness of nodes sampled. In this paper, we propose a churn adaptive approach to network size estimation - CANSE, which collects closest nodes in identification to each node's identification by sampling nodes periodically. Each node collects closest identifications by two schemes. One scheme is sampling random nodes from random walks along the topology. The other one is exchanging the closest identifications with other nodes. Finally, each node calculates the average spacing of the closest identifications collected to estimate network size. Compared with existing approaches, extensive experiments show that CANSE provides accurate estimation values quickly in various dynamic topologies. © 2010 IEEE.

关键词： Topology

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Power analysis and optimizations for GPU architecture using a power simulator

Power analysis and optimizations for GPU architecture using ...

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2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010

作者： Wang, Guibin National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781424465408

As one of the most popular many-core architecture, GPUs have illustrated power in many non-graphic applications. Traditional general purpose computing systems tend to integrate GPU as the co-processor to accelerate parallel computing tasks. Meanwhile, GPUs also result in high power consumption, which accounts for a large proportion of the total system power consumption. In this paper, we mainly focus on the power analysis and optimizations for GPU architecture. The main contributions of this paper are: firstly, we establish a GPU power reserach platform, which is extended from an existing GPU simulator with several power models;secondly, we validate that, as the gap between shader core and memory speed becomes larger and larger, integrating more shader cores or enhancing running frequencies may not bring better performance, but results in higher energy consumption;thirdly, we show that traditional power optimization methods for CPUs, such as dynamic frequency scaling and concurrencythrottling, could be effectively applied on GPU architectures for better power efficiency, especially for memory-intensive applications. © 2010 IEEE.

关键词： Simulators

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nSET: Novel Simulation Method for Single-Electron Tunnel Device with 1-Dimension Multiple Islands

nSET: Novel Simulation Method for Single-Electron Tunnel Dev...

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3rd IEEE International NanoElectronics Conference (INEC)/Symposium on Nanoscience and Nanotechnology in China

作者： Sui, Bingcai Chi, Yaqing Fang, Liang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan 410073 China National University of Defense Technology China

ISBN: (纸本)9781424435432

Single-electronic transistors (SETs) are considered as the attractive candidates for post-COMS VLSI due to their ultra-small size and low power consumption. Because SETs with single island can not work at room temperature normally, more and more researchers begin to make research on the SETs with 1-dimension multi-islands. A new simulation method-nSET, is introduced in this paper Compared with other methods, nSET can simulate the SET device with 1-Dimension multiple islands with high speed and accuracy. Through the comparison, it can be get that nSET is accurate and fast compared with the classical Monte Carlo(MC) simulator, and is very useful for the ASIC design of SET devices.

关键词： Monte Carlo simulation single-electron tunneling device single-electron transistor multiple islands

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Media access control protocol based on hybrid antennas in ad hoc networks

Media access control protocol based on hybrid antennas in ad...

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International Conference on Autonomic and Trusted Computing

作者： Ding, Yanrong Wang, Xiaodong Shen, Hu Guo, Pengyu National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769542720

Nested Circular Directional MAC, a modified medium access control protocol of DMAC protocol, is proposed in this paper to support both directional antennas and omni-directional antennas simultaneously in one Ad Hoc network. Omni-directional antennas follow the RTS/CTS mechanism which is multi-hop and directional antennas follow the DRTS/DCTS mechanism, ensuring the asymmetric communication effectively. In order to resolve new deafness problem and hidden terminal problem, the directional antennas also use circular DRTS and nested antenna circumrotation. Simulation results show that NCDMAC supports hybrid antennas effectively and is better than MMAC and Circular-MAC in terms of increasing throughput, but it also increases the communication delay. © 2010 IEEE.

关键词： Ad hoc networks

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Sim-spm: A simplescalar-based simulator for multi-level SPM memory hierarchy architecture

Sim-spm: A simplescalar-based simulator for multi-level SPM ...

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IEEE International Conference on High Performance Computing and Communication

作者： Ren, Xiaoguang Tang, Yuhua Tang, Tao Ye, Sen Wang, Huiquan Zhou, Jing National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan 410073 China

ISBN: (纸本)9780769542140

As a fast on-chip SRAM managed by software (the application and/or compiler), Scratchpad Memory (SPM) is widely used in many fields. This paper presents a SimpleScalar-based multi-level SPM memory hierarchy architecture simulator Sim-spm. We simulate the hardware of the multi-level SPM memory hierarchy successfully by extending Sim-outorder, which is an out-of-order simulator from SimpleScalar. Through the simulating memory method, the simulation framework of the multi-level SPM memory hierarchy has been built under the existing ISA (Instruction Set Architecture), which largely reduces the requirement to modify the existing compiler. The experimental results show that Sim-spm can accurately simulate the running state of the processor with a multi-level SPM memory hierarchy architecture, and it has a good prospect for the research of multi-level SPM memory hierarchy architecture. © 2010 IEEE.

关键词： Simulators

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Metal interference analysis and design rules of on chip antennas for wireless interconnect

Metal interference analysis and design rules of on chip ante...

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International Symposium on Signals, Systems and Electronics

作者： He, Xiaowei Zhang, Minxuan Li, Jinwen Li, Shaoqing National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan 410073 China

ISBN: (纸本)9781424463558

The influence of on-chip metal interconnections, power grids, heat sink together with packaging, and metal dummy fills on the transmission characteristics of a 2mm-long integrated dipole antenna pair has been investigated in this paper. These metal structures and placements have been classified and particular simulations are performed to explore the interference effects of neighboring various metal structures on transmission gain, phase, impedance and radiation pattern for on-chip dipole antenna pair. By virtue of the experimental results and analyses, several experiential linear expressions for antenna pair gain and phase in interference circumstances are obtained using numerical fit. A set of design rules is concluded accordingly for guiding on-chip antenna layout and design targeting wireless interconnect. © 2010 IEEE.

关键词： Dipole antennas

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A distributed Approach to Consistent Order Delivery of Concurrent Events in Asynchronous DVEs

A Distributed Approach to Consistent Order Delivery of Concu...

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2010 2nd International Conference on Education technology and Computer(第二届IEEE教育技术与计算机国际会议 ICETC 2010)

作者： Hangjun Zhou Wei Zhang Yuxing Peng Sikun Li Key Laboratory of Science and Technology for National Defence of Parallel and Distributed Processing Key Laboratory of Science and Technology for National Defence of Parallel and Distributed Processing

ISBN: (纸本)9781424463671;9781424463688;9781424463701

In large-scale asynchronous distributed virtual environments(DVEs), one of the difficult problems is to deliver the concurrent events in a consistent order at each node. Generally, the previous consistency control approaches can be classified into two categories: causal order and time stamped order. However, causal order approaches can merely preserve the cause-effect relation of events and time stamped order approaches seem intrinsically complex to be used in serverless large-scale asynchronous DVEs. In this paper, we proposed a novel distributed algorithm to identify the concurrent events and preserve the consistent order delivery of them at different nodes. Simulation studies are also carried out to compare the performance of this algorithm with that of the previous ones. The results show that the new algorithm can effectively deliver the concurrent events in consistent order at each node and is more efficient than the previous algorithms in large-scale asynchronous DVEs.

关键词： distributed virtual environments concurrent events distributed consistency algorithm

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RETRACTED ARTICLE: parallel block multigrid preconditioner for 3D navier-stokes equations on unstructured grids

RETRACTED ARTICLE: Parallel block multigrid preconditioner f...

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作者： Li, Zongzhe Lu, Yao Cao, Wei Wang, Yongxian Wang, Zhenghua Parallel and Distributed Processing for National Laboratory School of Computer Science National University of Defence Lechnology Changsha Hunan 410073 China

ISBN: (纸本)9781424472369

In this paper, we explore a parallel block multigrid preconditioner based on factorization of the coefficient matrix generated in three-dimensional unstructured grids system. This preconditioner is robust with respect to the magnitude of the mesh size and the coefficient complexity, apply smoothed aggregation algebraic multigrid which using block lower-upper symmetric Gauss-Seidel(BLU-SGS) as smoother to accelerate convergent rate. We focus on this method to three-dimensional, unstructured, large-scale, parallel and NS equations' steady-state simulations. The numerical results which conducted on NACA0012 airfoil indicate that nearly optimal convergence rates and computational complexity for parallel solutions, this method also provide high speedup and efficiency for a series of processors. © 2010 IEEE.

关键词： Navier Stokes equations

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A load balancing-supported constant degree DHT ID assignment method

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Tien Tzu Hsueh Pao/Acta Electronica Sinica 2010年第11期38卷 2649-2654页

作者： Wang, Xiao-Hai Peng, Yu-Xing Li, Dong-Sheng Key Laboratory of Science and Technology for Parallel and Distributed Processing National University of Defense Technology Changsha Hunan 410073 China

A Load Balancing-Supported ID assignment method is the foundation to implement and maintain DHT overlays, realized constant degree DHTs usually use simple pure centralized or distributed ID management strategies, which cannot resolve the contradiction between cost of maintaining topologies' information and topologies' balance. Analyzing the universal tree structures in the topologies, an ID Assignment method RFIDAM based on the internal structure Routing Forest is proposed, which regularly aggregates local balancing information to guide new nodes' joining for overall balance. The experimental results show, with low maintenance and routing message overhead, the system's loading balance is efficiently ensured with the length of IDs differ by at most 2.

关键词： Topology

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