A silicon carbide (SiC) vertical channel junction field effect transistor (VJFET) was fabricated based on in-house SiC epitaxial wafer with lift-off trenched and implanted method. Its blocking voltage exceeds 1300V at...
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Fabrication, characterization, and modeling of on-chip integrated inductors with magnetic thin film (NiFe-SiOX) on sapphire-based GaN substrate was reported. The fabrication processes were compatible with the conventi...
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A submicron InGaAs/InP DHBT fabricated using triple mesa structure and BCB planarization technology is presented. All processes are on 3-inch wafers. The DHBT with emitter area of 0.7×10μm2 exhibits a current cu...
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A common base four-finger InOaAs/InP double heterojunction bipolar transistor with 535 OHz fmax by using the 0.5 μm emitter technology is fabricated. Multi-finger design is used to increase the input current. Common ...
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A common base four-finger InOaAs/InP double heterojunction bipolar transistor with 535 OHz fmax by using the 0.5 μm emitter technology is fabricated. Multi-finger design is used to increase the input current. Common base configuration is compared with common emitter configuration, and shows a smaller K factor at high frequency span, indicating a larger breakpoint frequency of maximum stable gain/maximum available gain (MSG/MAG) and thus a higher gain near the cut-off frequency, which is useful in THz amplifier design.
We present high-performance enhancement-mode AlGaN/GaN metal-oxide-semiconductor highelectron mobility transistors(MOS-HEMTs) by a fluorinated gate dielectric technique.A nanolaminate of an Al_2O_3/La_xAl_(1-x)O_3...
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We present high-performance enhancement-mode AlGaN/GaN metal-oxide-semiconductor highelectron mobility transistors(MOS-HEMTs) by a fluorinated gate dielectric technique.A nanolaminate of an Al_2O_3/La_xAl_(1-x)O_3/Al_2O_3 stack(x≈0.33) grown by atomic layer deposition is employed to avoid fluorine ions implantation into the scaled barrier *** enhancement-mode MOS-HEMTs exhibit an excellent performance as compared to those with the conventional dielectric-last technique,delivering a large maximum drain current of 916 mA/mm and simultaneously a high peak transconductance of 342 mS/*** balanced DC characteristics indicate that advanced gate stack dielectrics combined with buffered fluorine ions implantation have a great potential for high speed GaN E/D-mode integrated circuit applications.
High quality Al0.3Ga0.7N/GaN/Al0.04Ga 0.96N double heterostructure was grown by metal-organic chemical vapor deposition (MOCVD). Two kinds of fabrication technology of Ka band GaN HEMT devices were developed. Using de...
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In this paper, we analyzed the technology of mm-wave power amplifier MMIC. We developed mm-wave GaAs pHEMT with a power density of 0.6W/mm at 35GHz. A fully monolithic 4-stage 4W mm-wave power amplifier was designed a...
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Epitaxial GaAs-on-Si is an ideal material system for studying the physics of mismatched heteroepitaxy of a polar semiconductor layer grown on a non-polar substrate like silicon. Understanding and optimization of the i...
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We report excellent dc and RF performance of high-linearity AIGaN/GaN FinFETs with 100 nm T-gate. Besides a high fT of 65 GHz enabled by scaled gate length, good linearity characteristics of Gm and fT/fmax are demonst...
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High voltage 4H-SiC junction barrier schottky (JBS) diode with breakdown voltage higher than 4.5 kV has been fabricated. The doping level and thickness of the N-type drift layer and the device structure have been perf...
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