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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： A.J. van de Goor I. Schanstra Department of Information Technology and Systems Section Computer Engineering Delft University of Technnology Delft Netherlands Infineon Technologies Munich Germany

ISBN: (纸本)0769514537

The way address sequences and data patterns appear on the outside of a memory may differ from their internal appearance; this effect is referred to as scrambling, which has a large impact on the effectiveness of the used tests. This paper presents an analysis of address and data scrambling for memory chips, at the layout and at the electrical level. A method is presented to determine the data backgrounds to be used for the different memory tests. It will be shown that the required data backgrounds are fault model, and hence, also test specific. Industrial results will show the influence of the used data backgrounds on the fault coverage of the tests.

关键词： Logic testing Electronic switching systems System testing information technology Data engineering systems engineering and theory Hip Design methodology Fault detection Cause effect analysis

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March SS: a test for all static simple RAM faults

March SS: a test for all static simple RAM faults

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IEEE International Workshop on Memory technology, Design and Testing

作者： S. Hamdioui A.J. van de Goor M. Rodgers Intel Corporation Santa Clara CA USA Faculty of Information Technology and Systems Computer Engineering Laboratory Delft University of Technnology Delft Netherlands

This paper presents all simple (i.e., not linked) static fault models that have been shown to exist for random access memories (RAMs), and shows that none of the current industrial march tests has the capability to detect all these faults. It therefore introduces a new test (March SS), with a test length of 22n, that detects all realistic simple static faults in RAMs.

关键词： Circuit faults Circuit testing Fault detection Random access memory Ultra large scale integration Electrical fault detection Semiconductor device testing Costs Coupling circuits Read-write memory

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Minimal Test for Coupling Faults in Word-Oriented Memories 02

Minimal Test for Coupling Faults in Word-Oriented Memories

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Proceedings of the conference on Design, automation and test in Europe

作者： A. van de Goor M. Abadir A. Carlin Delft University of Technology Department of Information Technology and Systems Section Computer Engineering Mekelweg 4 2628 CD Delft The Netherlands Motorola Test and Logic Verification 6200 Bridgepoint Parkway Bldg 4 Austin TX

ISBN: (纸本)9780769514710

Most industrial memories have an external word-width of more than one ***, most published memory test algorithms assume 1-bit memories; they will not detect coupling faults between the cells of a *** paper improves upon the state of the art in testing word-oriented memories by presenting a new method for detecting state coupling faults between cells of the same word, based on the use of m-out-of-n *** result is a reduction in test time, which varies between 20 and 38%.

关键词： State coupling faults

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A comparative study on the coherent approaches to cooperation between TCP and ATM congestion control algorithms

A comparative study on the coherent approaches to cooperatio...

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International Conference on computer Communications and Networks (ICCCN)

作者： Qing Yu D.B. Hoang D.D. Feng School of Information Technologies University of Sydney Sydney Australia Department of Computer Systems Faculty of IT University of Technology Sydney Australia Department of Electronic and Information Engineering Hong Kong Polytechnic University Hong Kong China

Numerous studies have indicated that ATM available bit rate (ABR) service can provide low-delay, fairness, and high throughput, and can handle congestion effectively inside the ATM network. However, network congestion is not really eliminated but rather it is pushed out to the edge of the ATM network, packets from TCP sources competing for the available ATM bandwidth are buffered in the routers or switches at the network edges, causing severe congestion, degraded throughput, and unfairness. This poor performance is mainly due to the uncoordinated interaction between the congestion control mechanism of TCP and ATM. It is well accepted that some form of cooperation at edge device would help to control TCP traffic flow over ATM more effectively. We have previously proposed the fair intelligent explicit window adaptation (FIEWA) scheme and fair intelligent ACK bucket control (FIABC) scheme. The key idea is to combine the feedback information from the receiver, from the underlying ATM network, and from the local information at the edge device intelligently to explicitly/implicitly control the TCP rate. We present a comparative simulation study on our schemes with other established schemes; to identify the characteristics of each different scheme; and to indicate the requirement for a fairer, simpler and more robust coherent approach at the edge device.

关键词： Asynchronous transfer mode Throughput Bit rate Bandwidth Packet switching Switches Degradation Communication system traffic control Intelligent control Feedback

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Effect of filament sausaging on current-voltage characteristics in a superconducting Bi-2223 tape

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AIP Conference Proceedings 2002年第1期614卷 1110-1117页

作者： Y. Ueno E. S. Otabe T. Matsushita M. Kiuchi 1Faculty of Computer Science and Systems Engineering Kyushu Institute of Technology 680-4 Kawazu Iizuka 820-8502 Japan 2Graduate School of Information Science and Electronic Engineering Kyushu University 6-10-1 Hakozaki Higashi-ku Fukuoka 812-8581 Japan

The current-voltage characteristics of superconducting Bi-2223 tapes are not as sharp as those of metallic superconductors. This feature, characterized by their low n values especially at high fields and at high temperatures, is partly influenced by the sausaging of the superconducting filaments. In order to improve the n values, therefore, the effect of filament sausaging on the transport property was investigated in this research. It was found that the distribution of the thickness of the filaments is of a Gaussian type. The real distribution of the critical current density (Jc) is obtained from the thickness distribution and the apparent distribution of pinning strength estimated using the flux creep-flow model. The estimated real distribution of Jc is slightly sharper than the apparent distribution of Jc. However, the improvement of the n-value is predicted not to be remarkable, even if the filament thickness can be made uniform.

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Dependence of irreversibility and vortex glass-liquid transition fields on electric field criterion in a superconducting Bi-2223 tape

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AIP Conference Proceedings 2002年第1期614卷 1193-1200页

作者： T. Matsushita M. Fukuda T. Kodama E. S. Otabe M. Kiuchi T. Kiss T. Akune N. Sakamoto K. Itoh 1Faculty of Computer Science and Systems Engineering Kyushu Institute of Technology 680-4 Kawazu Iizuka 820-8502 2Graduate School of Information Science and Electronic Engineering Kyushu University 6-10-1 Hakozaki Higashi-ku Fukuoka 812-8501 Japan 3Faculty of Engineering Kyushu Sangyo University 3-1 Matsukadai 2 chome Higashi-ku Fukuoka 813-8503 Japan 4National Institute for Materials Science 1-2-1 Sengen Tsukuba-shi Ibaraki 305-0047 Japan

It is known that the irreversibility field depends largely on the electric field criterion, Ec, for the determination of the critical current density. In addition, it was recently found that the vortex glass-liquid transition field determined by the scaling of current-voltage curves also depended on the range of electric field in the measurement. In this paper the two characteristic fields are measured for a Bi-2223 silver-sheathed tape as a function of the electric field. The obtained result of the irreversibility field is compared with the theoretical result of the flux creep-flow model. Based on the agreement with the theoretical model a standard test method of the irreversibility field is proposed.

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VLSI architecture of burst mode acceleration for 128-bit block ciphers

VLSI architecture of burst mode acceleration for 128-bit blo...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Y. Mitsuyama Z. Andales T. Onoye I. Shirakawa I. Arungsrisangchai Dept. Information Systems Eng. Osaka University Japan Institute of MSP University of the Philippines at Los Banos Los Banos Philippines Dept. Comm. & Computer Eng. Kyoto University Japan Faculty of Engineering King Mongkut''s Institute of Technology Ladkrabang Thailand Faculty of Eng. King Monakut's Institute of Technologv Ladkrabang Thailand

"Burst mode" is a new cipher mode, which is devised dedicatedly for the high performance implementation of the Advanced Encryption Standard (AES) and other next generation 128-bit block cipher algorithms. In comparison with the conventional modes, the burst mode achieves a considerable increase in the throughput by employing a novel stream cipher mechanism which can encrypt 64 plaintext blocks through 16 times of block cipher encryptions. This paper presents a high performance VLSI architecture of burst mode implemented as an accelerator core running in parallel with a block cipher in software. Implementation results show that this burst mode with the use of this hardware accelerator raises the speed of the software implementation by four times, achieving a maximum rate of 3.4 Gbps.

关键词： Very large scale integration Acceleration Cryptography Throughput computer architecture Hardware Output feedback Costs information systems High performance computing

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On the construction of monitors for temporal logic properties

On the construction of monitors for temporal logic propertie...

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RV'2001, Runtime Verification (in Connection with CAV '01)

作者： Geilen, Marc Section of Information and Communication Systems Faculty of Electrical Engineering Eindhoven University of Technology Eindhoven Netherlands

Temporal logic is a valuable tool for specifying correctness properties of reactive programs. With the advent of temporal logic model checkers, it has become an important aid for the verification of concurrent and reactive systems. In model checking the temporal logic properties are verified against models expressed in the tool's modelling language. In addition, model-checking techniques are useful to test actual implementations or to verify models of the system that are too detailed to be analysed by a model checker, by means of, for instance, simulation. A tableau construction is an algorithm that translates a temporal logic formula into a finite-state automaton that accepts precisely all the models of the formula. It is a key ingredient to checking satisfiability of a formula as well as to the automata-theoretic approach to model checking. An improvement to the efficiency of tableau constructions has been the development of on-the-fly versions. In this paper, we present a particular tableau construction for the incremental analysis of execution traces during test, simulation or model-checking. The automaton forms the basis of a monitor that detects both good and bad prefix of a particular kind, namely those that are informative for the property under investigation. We elaborate on the construction of the monitor and demonstrate its correctness. © 2001 Published by Elsevier Science B.V.

关键词： Formal logic

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Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs

Static and dynamic behavior of memory cell array opens and s...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Z. Al-Ars A.J. van de Goor Section Computer Engineering Faculty of Information Technology and Systems Delft University of Technnology Delft Netherlands

ISBN: (纸本)0769509932

Fault analysis of memory devices using defect injection and simulation is becoming increasingly important as the complexity of memory faulty behavior increases. In this paper this approach is used to study the effects of opens and shorts on the faulty behavior of embedded DRAM (eDRAM) devices produced by Infineon Technologies. The analysis shows the existence of previously defined memory fault models, and establishes new ones. The paper also investigates the concept of dynamic faulty behavior and establishes its importance for memory devices. Conditions to test the newly established fault models are also given.

关键词： Random access memory Testing Analytical models Manufacturing Fault detection Circuit faults Circuit simulation Embedded computing information technology information analysis

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Transient faults in DRAMs: concept, analysis and impact on tests

Transient faults in DRAMs: concept, analysis and impact on t...

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IEEE International Workshop on Memory technology, Design and Testing

作者： Z. Al-Ars A.J. van de Goor Section Computer Engineering Faculty of Information Technology and Systems Delft University of Technnology Delft Netherlands

Memory fault models have always been considered not to change with time. Therefore, tests constructed to detect sensitized faults need not take into consideration the time period between sensitizing and detecting the fault. In this paper; a new class of memory fault models is presented, where the time between sensitizing and detection should be considered. The paper also presents fault analysis results, based on defect injection and simulation, where transient faults have been observed. The impact of transient faults on testing is discussed and new detection conditions, in combination with a test, are given.

关键词： Transient analysis Random access memory Testing information technology Capacitors Thin film transistors

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