Temporal logic is a valuable tool for specifying correctness properties of reactive programs. With the advent of temporal logic model checkers, it has become an important aid for the verification of concurrent and rea...
Temporal logic is a valuable tool for specifying correctness properties of reactive programs. With the advent of temporal logic model checkers, it has become an important aid for the verification of concurrent and reactive systems. In model checking the temporal logic properties are verified against models expressed in the tool's modelling language. In addition, model-checking techniques are useful to test actual implementations or to verify models of the system that are too detailed to be analysed by a model checker, by means of, for instance, simulation. A tableau construction is an algorithm that translates a temporal logic formula into a finite-state automaton that accepts precisely all the models of the formula. It is a key ingredient to checking satisfiability of a formula as well as to the automata-theoretic approach to model checking. An improvement to the efficiency of tableau constructions has been the development of on-the-fly versions. In this paper, we present a particular tableau construction for the incremental analysis of execution traces during test, simulation or model-checking. The automaton forms the basis of a monitor that detects both good and bad prefix of a particular kind, namely those that are informative for the property under investigation. We elaborate on the construction of the monitor and demonstrate its correctness.
The ability to autonomously generate and execute large angle attitude maneuvers, while operating under a number of celestial and dynamical constraints, is a key factor in the development of several future space platfo...
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This paper begins with a brief overview of realistic fault models for multi-port SRAMs with p ports, divided into p classes: single-port faults, two-port faults,..., p-port faults. Except for single-port faults, all o...
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ISBN:
(纸本)0769513786
This paper begins with a brief overview of realistic fault models for multi-port SRAMs with p ports, divided into p classes: single-port faults, two-port faults,..., p-port faults. Except for single-port faults, all other fault classes cannot be detected with the conventional (single-port) memory tests; they require special tests. Next, the paper presents a set of three linear single-addressing tests for unique multi-port memory faults (p > 2) that will be merged into a single test.
Temperature has proven to be an effective stress condition, commonly used to stress memory devices and to detect special types of failure mechanisms. In this paper a new approach is presented where temperature is used...
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Temperature has proven to be an effective stress condition, commonly used to stress memory devices and to detect special types of failure mechanisms. In this paper a new approach is presented where temperature is used as a test parameter to increase the fault coverage of specific tests. This is done using defect injection and simulation of a memory model at different temperatures. The analysis presents new types of detection conditions for memories and evaluates the impact of temperature on these conditions.
Presents a complete analysis, at the electrical level, of address decoder faults caused by resistive opens, and by capacitive-coupling between address lines. Several authors have demonstrated the importance of this cl...
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ISBN:
(纸本)0769513786
Presents a complete analysis, at the electrical level, of address decoder faults caused by resistive opens, and by capacitive-coupling between address lines. Several authors have demonstrated the importance of this class of faults. New test conditions, and new march tests are derived to detect the resulting faults; and industrial results, applied to DRAMS, show the effectiveness of the new tests.
This paper shows the shortcomings of the current, generic notation for fault models and extends it to allow the description of fault models for DRAMs. The advantage is that the extended fault models can easily be tran...
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ISBN:
(纸本)0769513786
This paper shows the shortcomings of the current, generic notation for fault models and extends it to allow the description of fault models for DRAMs. The advantage is that the extended fault models can easily be translated into operation sequences and tests that detect the described fault. Examples are given to show that the new notation results in optimized, memory specific, tests that have a shorter run time for a given fault coverage.
Program slicing has many applications in software engineering activities. However, until recently, no slicing algorithm has been presented that can compute executable slices for concurrent logic programs. We present a...
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ISBN:
(纸本)0769512879
Program slicing has many applications in software engineering activities. However, until recently, no slicing algorithm has been presented that can compute executable slices for concurrent logic programs. We present a dependence-graph based approach to computing executable slices for concurrent logic programs. The dependence-based representation used in the paper is called the Argument Dependence Net which can be used to explicitly represent various types of program dependences in a concurrent logic program. Based on the ADN, we can compute static executable slices for concurrent logic programs at argument level.
Object technology is an approach that is increasingly being adopted for the development of quality software and software-intensive systems. Recent experience has demonstrated that it provides a sophisticated environme...
ISBN:
(纸本)9780769510507
Object technology is an approach that is increasingly being adopted for the development of quality software and software-intensive systems. Recent experience has demonstrated that it provides a sophisticated environment to support high quality software engineering practice. However, the use of object technology should not be restricted to languages but should encompass analysis, design, V&V and many such aspects belonging to the methodological dimension of the development life-cycle. Furthermore, it should also cover other issues belonging to the technological and contextual aspects.
In this paper, we propose a method for detecting a traffic sign from a scene image in the daytime. This method uses Active Net in two steps. Active net is a deformable lattice network model which minimizes an energy f...
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In this paper, we propose a method for detecting a traffic sign from a scene image in the daytime. This method uses Active Net in two steps. Active net is a deformable lattice network model which minimizes an energy function to detect the region of a target object. In the proposed method, the first Active Net roughly estimates a position of a target region For the better target detection, we put the second Active Net around the estimated position. However, since the number of the iteration of Active Net is fixed, an unnecessary computation is performed in the method Therefore, a method to exclude unnecessary computation by automatic stopping of Active Net is also proposed. Experimental results show the effectiveness and efficiency of the proposed method.
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