A new hardware structure for implementation of soft morphological filters is presented in this paper. This is based on the modification of the majority gate technique. A pipelined systolic array architecture suitable ...
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SHE (software/hardware engineering) is a new object-oriented analysis, specification and design method for complex reactive hardware/software systems. SHE is based on the formal specification language POOSL and a desi...
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SHE (software/hardware engineering) is a new object-oriented analysis, specification and design method for complex reactive hardware/software systems. SHE is based on the formal specification language POOSL and a design framework for guiding analysis and design activities. This paper reports on the applicability of the SHE method for the specification and design of the control subsystem of a new generation of industrial mailing machines.
In this paper is presented a new approach to robust non-linear control design, which can guarantee a prescribed decay rate of exponential stability for known system uncertainties. The proposed approach doesn’t employ...
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In this paper is presented a new approach to robust non-linear control design, which can guarantee a prescribed decay rate of exponential stability for known system uncertainties. The proposed approach doesn’t employ matching conditions. The non-linear power system with deterministic uncertainties is chosen as demonstration example.
This paper presents the design of a low cost, test processor ASIC chip implementing multiple seed, multiple polynomial linear feedback shift register (MPMSLFSR). User programmable seed and feedback connection can be s...
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This paper presents the design of a low cost, test processor ASIC chip implementing multiple seed, multiple polynomial linear feedback shift register (MPMSLFSR). User programmable seed and feedback connection can be set in the pattern generator of the chip to improve fault coverage. The ASIC also supports scan-path testing. It can also be used to design external IC tester.
We relate the H/sub /spl infin// and H/sub 2/ norms for multi-input/multi-output sampled-data feedback control systems, where a continuous-time plant is controlled by a digital compensator with hold and sampler. Upper...
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We relate the H/sub /spl infin// and H/sub 2/ norms for multi-input/multi-output sampled-data feedback control systems, where a continuous-time plant is controlled by a digital compensator with hold and sampler. Upper bounds on both H/sub 2/ and H/sub /spl infin// norms are obtained based on fundamental relations derived by two different approaches, namely the hybrid state-space approach and the fast sampling and lifting approach.
Since the layout compaction problem is dual to the minimum cost flow problem, flow algorithms can be applicable to the layout compaction. In this paper, an existing flow algorithm is investigated in terms of the layou...
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Since the layout compaction problem is dual to the minimum cost flow problem, flow algorithms can be applicable to the layout compaction. In this paper, an existing flow algorithm is investigated in terms of the layout compaction, and a fast flow algorithm is devised on the basis of the primal-dual method. Experimental results show that the proposed algorithm is the fastest dedicatedly for the compaction problem.
Usually, the subspace-based state-space system identification algorithms are focused on discrete-time models, which may cause some numerical problems when the sampling interval is small. This paper proposes an algorit...
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Usually, the subspace-based state-space system identification algorithms are focused on discrete-time models, which may cause some numerical problems when the sampling interval is small. This paper proposes an algorithm of subspace-based state-space system identification for continuous-time systems from sampled input-output data. The ω — operator ω = ( p - α)/( p + α) where p denotes a differential operator and α > 0, is introduced to avoid direct numerical differentiations. And the ω — operator state-space model identified by the 4SID method can be transformed back to the common continuous-time state-space model. The numerical superiority of the ω — operator approach compared to some other methods is verified through simulation study.
Hybrid simulation includes both functional computer software models and actual hardware subsystems operating as an integrated whole. A ''hot test bed'' or a ''hybrid simulator-emulator''...
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Hybrid simulation includes both functional computer software models and actual hardware subsystems operating as an integrated whole. A ''hot test bed'' or a ''hybrid simulator-emulator'' enables design engineers to evaluate conceptual models in a more realistic real-lime context, but places increased cognitive demands on the designer. This paper describes an architecture, and results from a prototype implementation, for a design decision support system to allow a designer to make more productive and cost effective use of a test bed system.
A prototype concurrent engineering tool has been developed for the preliminary design of composite topside structures for modern navy warships. This tool, named GELS for the Concurrent engineering of Layered Structure...
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A prototype concurrent engineering tool has been developed for the preliminary design of composite topside structures for modern navy warships. This tool, named GELS for the Concurrent engineering of Layered Structures, provides designers with an immediate assessment of the impacts of their decisions on several disciplines which are important to the performance of a modern naval topside structure, including electromagnetic interference effects (EMI), radar cross section (RCS), structural integrity, cost, and weight. Preliminary analysis modules in each of these disciplines are integrated to operate from a common set of design variables and a common materials database. Performance in each discipline and an overall fitness function for the concept are then evaluated. A graphical user interface (GUI) is used to define requirements and to display the results from the technical analysis modules. Optimization techniques, including feasible sequential quadratic programming (FSQP) and exhaustive search are used to modify the design variables to satisfy all requirements simultaneously. The development of this tool, the technical modules, and their integration are discussed noting the decisions and compromises required to develop and integrate the modules into a prototype conceptual design tool.
The design and VLSI implementation of a new ASIC which performs the operation of grey-scale dilation using both image and structuring element threshold decomposition is presented in this paper. The minimum rate of ext...
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The design and VLSI implementation of a new ASIC which performs the operation of grey-scale dilation using both image and structuring element threshold decomposition is presented in this paper. The minimum rate of external operations of this ASIC is 30 MPix/sec and it can handle 3 x 3 pixel images and structuring elements of up to 4-bit resolution. The high speed of operation is achieved using the pipelining technique. The ASIC is implemented using a DLM, 1.0 mu m, N-well, CMOS process provided by the European Silicon Structures (ES2), and it occupies a silicon area of 5.48 x 5.77 mm = 31.61 mm(2). It is intended to be used in machine vision applications, where the need for short processing times is crucial (e.g. robotics and military systems).
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