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检索条件"机构=Section Digital Systems and Computer Architecture"

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COMPARING SOFTWARE PIPELINING FOR AN OPERATION-TRIGGERED AND A TRANSPORT-TRIGGERED architecture 4th

COMPARING SOFTWARE PIPELINING FOR AN OPERATION-TRIGGERED AND...

引用

4TH INTERNATIONAL WORKSHOP ON COMPILER CONSTRUCTION ( CC 92 )

作者： HOOGERBRUGGE, J CORPORAAL, H Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems Netherlands

ISBN: (纸本)3540559841

This paper reports the results of a comparison between a new class of architectures, called transport-triggered architectures, and traditional architectures, called operation-t~iggered architectures. It does this comparison by means of the MOVE-i860, which is a transport-triggered approximation of the i860. Several benchmarks are scheduled for the MOVE-i860 by a software pipelining scheduler. By scheduling according to three scheduling disciplines, we are able to measure the advantages of transport-triggered architectures. The results of the experiments show that transport-triggered architectures perform better than operation-triggered architectures with similar hardware. © 1992, Springer Verlag. All rights reserved.

关键词： Scheduling

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Software pipelining for transport-triggered architectures 24

Software pipelining for transport-triggered architectures

引用

Proceedings of the 24th International Symposium on Microarchitecture - MICRO 24

作者： Hoogerbrugge, Jan Corporaal, Henk Mulder, Hans Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems

ISBN: (纸本)0897914600

This paper discusses software pipelining for a new class of architectures that we call transport-triggered. These architectures reduce the interconnection requirements between function units. They also exhibit code scheduling possibilities which are not available in traditional operation-triggered architectures. In addition the scheduling freedom is extended by the use of so-called hybridpipelined function utits. In order to exploit this tleedom, existing scheduling techniques need to be extended. We present a software pipelirtirtg technique, based on Lam's algorithm, which exploits the potential of !mnsport-triggered architectures. Performance results are presented for several benchmak loops. Depending on the available transport capacity, MFLOP rates may increase significantly as compared to scheduling without the extra degrees of freedom. © 1991 ACM.

关键词： Scheduling

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Use of CMOS technology in wave pipelining 5

Use of CMOS technology in wave pipelining

引用

5th International Conference on VLSI Design, ICVD 1992

作者： Klass, F. Mulder, J.M. Section Computer Architecture and Digital Systems Department of Electrical Engineering Delft University of Technology Netherlands

ISBN: (纸本)0818624655

Wave pipelining is a technique for pipelining digital systems that can increase the clock frequency without increasing the number of storage elements. This is achieved by clocking the system faster than the propagation delay between storage elements. The design of such systems is more difficult because all paths in the combinational logic must have about equal delay. To implement wave pipelining, some technologies seem to be better than others depending on the delay properties. Static CMOS has the disadvantage of pattern-dependent delay variations. This papers discusses the issues concerning the implementation of wave pipelining using CMOS technology. The maximum pipeline rate for a wave-pipelined circuit is calculated under data-dependent delay constraints. Bounding parameters to the system performance are provided. © 1991 IEEE.

关键词： Pipelines

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Transport-triggering vs. Operation-triggering 5th

Transport-triggering vs. Operation-triggering

引用

5th International Conference on Compiler Construction, CC 1994

作者： Hoogerbrugge, Jan Corporaal, Henk Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems Netherlands

ISBN: (纸本)9783662466629

Transport-triggered architectures are a new class of architectures that provide more scheduling freedom and have unique compiler optimizations. This paper reports experiments that quantify the advantages of transport-triggered architectures with respect to traditional operation-triggered architectures. For the experiments we use an extended basic block scheduler that is currently being developed. The paper gives an description of the scheduling techniques used. The results of our experiments show that the extra scheduling freedom together with the new optimizations are very welcome when resource constraints are limiting the performance. This is the case when resources are scarce or when the application contains a lot of instruction level parallelism. © Springer-Verlag Berlin Heidelberg 1994.

关键词： Scheduling

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Controlled node splitting 6th

引用

Proceedings of the 6th International Conference on Compiler Construction, CC'96

作者： Janssen, Johan Corporaal, Henk Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems 2600 GA Delft 5031 Netherlands

ISBN: (纸本)9783540610533

To exploit instruction level parallelism in programs over multiple basic blocks, programs should have reducible control flow graphs. However not all programs satisfy this property. A new method, called Controlled Node Splitting (CNS), for transforming irreducible control flow graphs to reducible control flow graphs is presented. CNS duplicates nodes of the control flow graph to obtain reducible control flow graphs. CNS results in a minimum number of splits and a minimum number of duplicates. Since the computation time to find the optimal split sequence is large, a heuristic has been developed. The results of this heuristic are close to the optimum. Straightforward application of node splitting may result in an average code size increase of 235%. CNS with the heuristic limits the increase to only 3%. © Springer-Verlag Berlin Heidelberg 1996.

关键词： Compilation Control flow graphs Instruction level parallelism Irreducibility Node splitting Reducibility

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Data buffering: run-time versus compile-time support

Data buffering: run-time versus compile-time support

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Third International Conference on Architectural Support for Programming Languages and Operating systems Architectural Support for Programming Languages and Operating systems

作者： Mulder, Hans Section Computer Architecture and Digital Systems Department of Electrical Engineering Delft University of Technology PO Box 5031 2600 AG Delft The Netherlands

ISBN: (纸本)0897913000

Data-dependency, branch, and memory-access penalties are main constraints on the performance of high-speed microprocessors. The memory-access penalties concern both penalties imposed by external memory (e.g. cache) or by under utilization of the local processor memory (e.g. registers). This paper focuses solely on methods of increasing the utilization of data memory, local to the processor (registers or register-oriented buffers).A utilization increase of local processor memory is possible by means of compile-time software, run-time hardware, or a combination of both. This paper looks at data buffers which perform solely because of the compile-time software (single register sets); those which operate mainly through hardware but with possible software assistance (multiple register sets); and those intended to operate transparently with main memory implying no software assistance whatsoever (stack buffers). This paper shows that hardware buffering schemes cannot replace compile-time effort, but at most can reduce the complexity of this effort. It shows the utility increase of applying register allocation for multiple register sets. The paper also shows a potential utility decrease inherent to stack buffers. The observation that a single register set, allocated by means of interprocedural allocation, performs competitively with both multiple register set and stack buffer emphasizes the significance of the conclusion

关键词： computer operating systems

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A flexible VLSI core for an adaptable architecture 22

A flexible VLSI core for an adaptable architecture

引用

22nd Annual Workshop on Microprogramming and Microarchitecture, MICRO 1989

作者： Mulder, Hans Stravers, Paul Section Digital Systems and Computer Architecture Department of Electrical Engineering Delft University of Technology P.O. Box 5031 Delft2600 GA Netherlands

ISBN: (纸本)0897913248

Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each architecture. The SCalable architecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific architectures;tools for synthesizing architectures from application or application-area;VLSI cell libraries and tools for quick generation of application-specific processors;a system-software platform which can be retargeted quickly to fit the application-specific architecture;This paper concentrates on the micro-architecture framework of SCARCE and outlines the process of generating VLSI processors. © 1990 ACM.

关键词： Cost effectiveness

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Cost-effective design of application specific VLIW processors using the SCARCE framework 22

Cost-effective design of application specific VLIW processor...

引用

22nd Annual Workshop on Microprogramming and Microarchitecture, MICRO 1989

作者： Mulder, Hans Portier, Robert J. Section Digital Systems and Computer Architecture Department of Electrical Engineering Delft University of Technology P.O. Box 5031 Delft2600 GA Netherlands

ISBN: (纸本)0897913248

Increasing the performance of application-specific processors by exploiting application-resident parallelism is often prohibited by costs;especially in the case of low-volume productions. The flexibility of horizontal-microcoded machines allows these costs to be reduced, but the flexibility often reduces efficiency. VLIW is a new and promising concept for the design of low-cost, high-performance parallel computer systems. We suggest that the VLIW concept can also be used as a basis for cost-effective design of application-specific processors which must exploit application-resident parallelism. The SCARCE (SCalable architecture Experiment) framework, an approach for cost-effective design of application-specific processors, provides features which allow the design of retargetable VLIW architectures. However, a retargetable VLIW architecture is only effective if there is a retargetable VLIW compiler. Since a VLIW compiler is an essential part of the VLIW architecture, tradeoffs must be made between the variety of VLIW architectures and the compiler complexity. We suggest that limiting the flexibility of the retargetable VLIW architecture does not necessary reduce the application space. This paper discusses the issues related to the design of a retargetable VLIW processor architecture and compiler within the SCARCE framework. © 1990 ACM.

关键词： Very long instruction word architecture

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DOAS: An object oriented architecture supporting secure languages 22

DOAS: An object oriented architecture supporting secure lang...

引用

22nd Annual Workshop on Microprogramming and Microarchitecture, MICRO 1989

作者： Van De Goor, A.J. Corporaal, H. Section Digital Systems and Computer Architecture Faculty of Electrical Engineering Delft University of Technology Mekelweg 4 P.O. Box 5031 Delft2600 AG Netherlands

ISBN: (纸本)0897913248

Current software engineering practice heavily relies on the reliability of software implementation languages and underlying architectures. However, both the currently used languages, as well as the traditional architectures suffer from a shortage of built-in security. In this paper, an architecture is presented, which is heavily influenced by two properties of secure languages: coercion and exception handling. It is shown that proper design decisions lead to an architecture having a compact data representation, allowing both generic and nongeneric instructions. The architecture is object oriented, and object addressing is under control of the operand stream, with optimalisation possibilities to bypass descriptor inspection. © 1990 ACM.

关键词： Object oriented programming

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A scalable VLSI MIMD routing cell 6

A scalable VLSI MIMD routing cell

引用

6th Distributed Memory Computing Conference, DMCC 1991

作者： Corporaal, H. Oik, J.G.E. Delft University of Technology Faculty of Electrical Engineering Section Computer Architecture and Digital Systems Mekelweg 4 P.O. Box 5031 GA Delft2600 Netherlands

ISBN: (纸本)0818622903

It is a well known fact that full custom designed computer architectures can achieve much higher performance for specific applications than general purpose computers. This performance has to be paid for: a long design trajectory results in a high cost-performance ratio. Current VLSI design and compilation tools however, make semi-custom designs feasible with greatly reduced costs and time to market. This paper presents a scalable and flexible communication processor for message passing MIMD systems. This communication processor is implemented as a parametri-sized VLSI routing cell in a VLSI compilation system. This cell fits into the SCARCE RISC processor framework [1], which is an architectural framework for automatic generation of application specific processors. By use of application analysis, the cell is tuned to the specific requirements during silicon compilation time. This approach is new, in that it avoids the general performance penalty paid for required flexibility. © 1991 IEEE.

关键词： Cells

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