This paper presents a structured way of deriving new functional fault models, based on the insertion of resistive defects into the electrical schematic of an SRAM. A taxonomy of the set of possible electrical faults i...
详细信息
This paper presents a structured way of deriving new functional fault models, based on the insertion of resistive defects into the electrical schematic of an SRAM. A taxonomy of the set of possible electrical faults is given, a set of primitive patterns to drive the electrical level simulator is derived, the existing notation for functional faults is revisited, and simulation results prove the existence of new functional faults.
A unidirectional flow systolic array with 100% efficiency is described for the linear discriminant classifier. To obtain this solution, a two-stage transformation method is applied to a contraflow array given by H.H. ...
详细信息
A unidirectional flow systolic array with 100% efficiency is described for the linear discriminant classifier. To obtain this solution, a two-stage transformation method is applied to a contraflow array given by H.H. Liu and K.S. Fu (1983). In the first stage, the contraflow design is transformed into an equivalent design with unidirectional flow. In the second stage, a retiming of input data sequences is performed and then combined with further refinements in the clocking scheme. As a result, the computational efficiency of the systolic array is significantly increased.< >
Most memory test algorithms are optimized tests for a particular memory technology, and a particular set of fault models, under the assumption that the memory is bit-oriented; i.e., read and write operations affect on...
详细信息
ISBN:
(纸本)9780818683596
Most memory test algorithms are optimized tests for a particular memory technology, and a particular set of fault models, under the assumption that the memory is bit-oriented; i.e., read and write operations affect only a single bit in the memory. Traditionally, word-oriented memories have been tested by repeated application of a test for bit-oriented memories whereby a different data background (which depends on the used intra-word fault model) is used during each iteration. This results in rime inefficiencies and limited fault coverage. A new approach for testing word-oriented memories is presented, distinguishing between inter-word and intra-word faults and allowing for a systematic way of converting tests for bit-oriented memories to rests for word-oriented memories. The conversion consists of concatenating the bit-oriented test for inter-word faults with a test for intra-word faults. This approach results in more efficient tests with complete coverage of the targeted faults. Because most memories have an external data path which is wider than one bit, word-oriented memory tests are very important.
Traditionally microcoded computers have been the ideal machines for implementing scalable architectures. These machines easily implement application-specific functionality in microcode and they allow architecturally t...
ISBN:
(纸本)9780818619199
Traditionally microcoded computers have been the ideal machines for implementing scalable architectures. These machines easily implement application-specific functionality in microcode and they allow architecturally transparent variation of cost/performance by trading off application code, microcode, and hardware. In contrast, hardwired machines are intrinsically incapable of implementing scalability, because they only implement a single level of interpretation. Recent RISC designs have introduced architectural features which partly resolve the scalability issues. They implement architectural openendness to allow application-specific functionality to be added to the architecture (by means of coprocessors and special function units). Additionally they define functions which, depending on application, cost, and performance, can be implemented in hardware or, by means of emulation, in *** identical from an abstract point of view, scalability by means of microprogramming and by means of emulation on a hardwired machine is significantly different. This paper describes the emulation facility provided in SCARCE (SCalable architecture Experiment), a streamlined architecture specifically designed for a wide range of embedded applications, requiring high performance. While architecturally transparent, this emulation facility operates with little overhead (8 cycles), adds three control registers, and is always interruptible. By increasing the hardware investment, the overhead could be decreased to 4 cycles per trap.
Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. Many two-port memories have ports which are read-only or wri...
详细信息
Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible tests for single-port and two-port memories, as well as the test strategy. This paper discusses the consequences of the port restrictions (read-only or write-only ports) on the tests; in addition it covers the test strategy for address decoder faults in two-port memories.
This paper describes the results of testing 50 single inline memory modules (SIMMs) each containing 16 16 Mbit DRAM chips (DUTs); 39 SIMMs failed, and of the 800 DUTs, 116 failed. In total 54 different test algorithms...
详细信息
This paper describes the results of testing 50 single inline memory modules (SIMMs) each containing 16 16 Mbit DRAM chips (DUTs); 39 SIMMs failed, and of the 800 DUTs, 116 failed. In total 54 different test algorithms have been applied, using up to 168 different stress combinations for each test. The results show that GAL9R is the best test. Furthermore, it is shown that burst mode tests detect a completely different class of faults as compared with traditional word mode tests, and that tests with address scrambling enabled the detection of more faults.
暂无评论