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March U: A test for unlinked memory faults

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 1997年第3期144卷 155-160页

作者： vandeGoor, AJ Gaydadjiev, GN Department of Electrical Engineering Section Computer Architecture & Digital Technique Delft University of Technology Mekelweg 4 Delft 2628 CD The Netherlands

Short and efficient memory tests is the goal of every test designer. To reduce the cost of production tests, often a simple test which covers most of the faults, e.g. all simple (unlinked) faults, is desirable to eliminate most defective parts;a more costly test can be used thereafter to eliminate the remainder of the bad parts. Such a test-cost efficient approach is used by most manufacturers. In addition, system power-on tests are not allowed a long test time while a high fault coverage is desirable. The authors propose a new realistic fault model (the disturb fault model), and a set of tests for unlinked faults. These tests have the property of covering all simple (unlinked) faults at a very reasonable test time compared with existing tests.

关键词： memory tests March tests memory faults fault model simple faults disturb fault

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Controlled node splitting 6th

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Proceedings of the 6th International Conference on Compiler Construction, CC'96

作者： Janssen, Johan Corporaal, Henk Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems 2600 GA Delft 5031 Netherlands

ISBN: (纸本)9783540610533

To exploit instruction level parallelism in programs over multiple basic blocks, programs should have reducible control flow graphs. However not all programs satisfy this property. A new method, called Controlled Node Splitting (CNS), for transforming irreducible control flow graphs to reducible control flow graphs is presented. CNS duplicates nodes of the control flow graph to obtain reducible control flow graphs. CNS results in a minimum number of splits and a minimum number of duplicates. Since the computation time to find the optimal split sequence is large, a heuristic has been developed. The results of this heuristic are close to the optimum. Straightforward application of node splitting may result in an average code size increase of 235%. CNS with the heuristic limits the increase to only 3%. © Springer-Verlag Berlin Heidelberg 1996.

关键词： Compilation Control flow graphs Instruction level parallelism Irreducibility Node splitting Reducibility

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Transport-triggering vs. Operation-triggering 5th

Transport-triggering vs. Operation-triggering

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5th International Conference on Compiler Construction, CC 1994

作者： Hoogerbrugge, Jan Corporaal, Henk Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems Netherlands

ISBN: (纸本)9783662466629

Transport-triggered architectures are a new class of architectures that provide more scheduling freedom and have unique compiler optimizations. This paper reports experiments that quantify the advantages of transport-triggered architectures with respect to traditional operation-triggered architectures. For the experiments we use an extended basic block scheduler that is currently being developed. The paper gives an description of the scheduling techniques used. The results of our experiments show that the extra scheduling freedom together with the new optimizations are very welcome when resource constraints are limiting the performance. This is the case when resources are scarce or when the application contains a lot of instruction level parallelism. © Springer-Verlag Berlin Heidelberg 1994.

关键词： Scheduling

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COMPARING SOFTWARE PIPELINING FOR AN OPERATION-TRIGGERED AND A TRANSPORT-TRIGGERED architecture 4th

COMPARING SOFTWARE PIPELINING FOR AN OPERATION-TRIGGERED AND...

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4TH INTERNATIONAL WORKSHOP ON COMPILER CONSTRUCTION ( CC 92 )

作者： HOOGERBRUGGE, J CORPORAAL, H Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems Netherlands

ISBN: (纸本)3540559841

This paper reports the results of a comparison between a new class of architectures, called transport-triggered architectures, and traditional architectures, called operation-t~iggered architectures. It does this comparison by means of the MOVE-i860, which is a transport-triggered approximation of the i860. Several benchmarks are scheduled for the MOVE-i860 by a software pipelining scheduler. By scheduling according to three scheduling disciplines, we are able to measure the advantages of transport-triggered architectures. The results of the experiments show that transport-triggered architectures perform better than operation-triggered architectures with similar hardware. © 1992, Springer Verlag. All rights reserved.

关键词： Scheduling

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Use of CMOS technology in wave pipelining 5

Use of CMOS technology in wave pipelining

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5th International Conference on VLSI Design, ICVD 1992

作者： Klass, F. Mulder, J.M. Section Computer Architecture and Digital Systems Department of Electrical Engineering Delft University of Technology Netherlands

ISBN: (纸本)0818624655

Wave pipelining is a technique for pipelining digital systems that can increase the clock frequency without increasing the number of storage elements. This is achieved by clocking the system faster than the propagation delay between storage elements. The design of such systems is more difficult because all paths in the combinational logic must have about equal delay. To implement wave pipelining, some technologies seem to be better than others depending on the delay properties. Static CMOS has the disadvantage of pattern-dependent delay variations. This papers discusses the issues concerning the implementation of wave pipelining using CMOS technology. The maximum pipeline rate for a wave-pipelined circuit is calculated under data-dependent delay constraints. Bounding parameters to the system performance are provided. © 1991 IEEE.

关键词： Pipelines

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CAD CAM GOES TO SEA - THE SAAR-5 DESIGN AND CONSTRUCTION

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NAVAL ENGINEERS JOURNAL 1992年第3期104卷 148-155页

作者： LINDGREN, JR SOLITARIO, WA MOORE, AP STREIFF, MA John R. Lindgren Jr:. is vice president for engineering at Ingalls Shipbuilding Inc. a Division of Litton Industries in Pascagoula Miss. He joined Ingalls in 1958 and has held various positions in the Engineering Division and participated in the design of numerous merchant ships drill rigs submarines and surface combatants and auxiliary support ships. Mr. Lindgren is a 1958 graduate of the University of Southwest Louisiana. His degree is in mechanical engineering and he is also a licensed professional engineer. William A. Solitario:is the director of advanced technology at Ingalls Shipbuilding Inc. in Pascagoula Miss. He received his B.S. degree in chemical engineering from the City University of New York and has 28 years experience in marine engineering and design. His current responsibilities include the direction of Ingalls' IRAD programs and several Navy-funded R&D programs to improve ship's performance and reduce ship's operating costs. He is a member of the Society of Naval Architects and Marine Engineers and past chairman of the Gulf Section East Area. Arnold P. Moore:is the director design engineering at Ingalls Shipbuilding where he is responsible for all new construction design and engineering activities. Prior to promotion to his current position Mr. Moore served as chief naval architect at Ingalls. He has 24 years experience in ship design construction and repair. Mr. Moore holds the professional degree of ocean engineer as well as a master's degree in naval architecture and marine engineering from MIT. He also earned a bachelor's degree in naval science from the U.S. Naval Academy and is a registered professional engineer. Mr. Moore served as an engineering duty officer in the U.S. Navy and is currently a captain in the Naval Reserve. He is a past chairman of the Gulf Section of the Society of Naval Architects and Marine Engineers and a member of the American Society of Naval Engineers and Sigma Xi. Michel A. Streiff:is the manager of CAD/CAM applications at Ingalls Shipbuilding Inc. His

The SA'AR-5 Corvette Program is the first major warship construction to be entirely accomplished using a 3-dimensional, interference checked computer based design. This paper discusses the organization and approach used to create the design models which form the basis for interference checking as well as the source of extracted production data. The design or product model is the nucleus of the computer data base that defines the configuration of the entire ship. The data base includes geometry, weight, and material, as well as production control data. The ability of the computer to link such diverse information is the key to maintaining configuration control during the course of the design and construction. The ease with which formatted manufacturing data (both N.C. fabrication and installation) can be extracted enables the preparation of detailed packages containing the desired geometry as well as the associated material and sequencing data, thus assuring the producibility of the design. The SA'AR-5 design is CAD/CAM's state of the art in U.S. shipbuilding.

关键词： Warships

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Software pipelining for transport-triggered architectures 24

Software pipelining for transport-triggered architectures

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Proceedings of the 24th International Symposium on Microarchitecture - MICRO 24

作者： Hoogerbrugge, Jan Corporaal, Henk Mulder, Hans Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems

ISBN: (纸本)0897914600

This paper discusses software pipelining for a new class of architectures that we call transport-triggered. These architectures reduce the interconnection requirements between function units. They also exhibit code scheduling possibilities which are not available in traditional operation-triggered architectures. In addition the scheduling freedom is extended by the use of so-called hybridpipelined function utits. In order to exploit this tleedom, existing scheduling techniques need to be extended. We present a software pipelirtirtg technique, based on Lam's algorithm, which exploits the potential of !mnsport-triggered architectures. Performance results are presented for several benchmak loops. Depending on the available transport capacity, MFLOP rates may increase significantly as compared to scheduling without the extra degrees of freedom. © 1991 ACM.

关键词： Scheduling

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Real realtime performance of heap management systems, using incremental copying collectors 24

Real realtime performance of heap management systems, using ...

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24th Annual Hawaii International Conference on System Sciences, HICSS 1991

作者： Corporal, H. Delft University of Technology Faculty of Electrical Engineering Section Computer Architecture and Digital Mekelweg 4 P.O. Box 5031 Delft2600 Netherlands

Realtime behaviour is normally associated with maximal response time in worst case situations. The author introduces a somewhat different notion of realtime behaviour, called realtime performance, which is based on an upperbound of the amount of time needed to acomplish a certain task. This concept is used to analyze the performance of incremental copying garbage collectors used in systems with automatic heap management. Traditionally those systems were considered unsuitable for realtime applications, either because of the inherent overhead of automatic collection, or because of the difficulty of implementing realtime collection on stock hardware. Recently however, an efficient implementation of incremental copying garbage collection was made, using stock hardware only. The combination of this method with the use of several object generations opens the world for realtime systems to use automatic collection. © 1991 IEEE.

关键词： Real time systems

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A scalable VLSI MIMD routing cell 6

A scalable VLSI MIMD routing cell

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6th Distributed Memory Computing Conference, DMCC 1991

作者： Corporaal, H. Oik, J.G.E. Delft University of Technology Faculty of Electrical Engineering Section Computer Architecture and Digital Systems Mekelweg 4 P.O. Box 5031 GA Delft2600 Netherlands

ISBN: (纸本)0818622903

It is a well known fact that full custom designed computer architectures can achieve much higher performance for specific applications than general purpose computers. This performance has to be paid for: a long design trajectory results in a high cost-performance ratio. Current VLSI design and compilation tools however, make semi-custom designs feasible with greatly reduced costs and time to market. This paper presents a scalable and flexible communication processor for message passing MIMD systems. This communication processor is implemented as a parametri-sized VLSI routing cell in a VLSI compilation system. This cell fits into the SCARCE RISC processor framework [1], which is an architectural framework for automatic generation of application specific processors. By use of application analysis, the cell is tuned to the specific requirements during silicon compilation time. This approach is new, in that it avoids the general performance penalty paid for required flexibility. © 1991 IEEE.

关键词： Cells

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Data buffering: run-time versus compile-time support

Data buffering: run-time versus compile-time support

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Third International Conference on Architectural Support for Programming Languages and Operating Systems Architectural Support for Programming Languages and Operating Systems

作者： Mulder, Hans Section Computer Architecture and Digital Systems Department of Electrical Engineering Delft University of Technology PO Box 5031 2600 AG Delft The Netherlands

ISBN: (纸本)0897913000

Data-dependency, branch, and memory-access penalties are main constraints on the performance of high-speed microprocessors. The memory-access penalties concern both penalties imposed by external memory (e.g. cache) or by under utilization of the local processor memory (e.g. registers). This paper focuses solely on methods of increasing the utilization of data memory, local to the processor (registers or register-oriented buffers).A utilization increase of local processor memory is possible by means of compile-time software, run-time hardware, or a combination of both. This paper looks at data buffers which perform solely because of the compile-time software (single register sets); those which operate mainly through hardware but with possible software assistance (multiple register sets); and those intended to operate transparently with main memory implying no software assistance whatsoever (stack buffers). This paper shows that hardware buffering schemes cannot replace compile-time effort, but at most can reduce the complexity of this effort. It shows the utility increase of applying register allocation for multiple register sets. The paper also shows a potential utility decrease inherent to stack buffers. The observation that a single register set, allocated by means of interprocedural allocation, performs competitively with both multiple register set and stack buffer emphasizes the significance of the conclusion

关键词： computer operating systems

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